參數(shù)資料
型號: MPC8241TVR200D
廠商: Freescale Semiconductor
文件頁數(shù): 15/58頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 200MHZ 357-PBGA
標準包裝: 44
系列: MPC82xx
處理器類型: 32-位 MPC82xx PowerQUICC II
速度: 200MHz
電壓: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應商設備封裝: 357-PBGA(25x25)
包裝: 托盤
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
22
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 11. Input/Output Timing Diagram Referenced to SDRAM_SYNC_IN
Figure 12. Input/Output Timing Diagram Referenced to PCI_SYNC_IN
11a
VM = Midpoint voltage (1.4 V).
Memory
10b-d
Inputs/Outputs
13b
14b
VM
SDRAM_SYNC_IN
Input Timing
Output Timing
12b-d
2.0 V
0.8 V
2.0 V
Tos
11a = Input hold time of SDRAM_SYNC_IN to memory.
12b-d = sys_logic_clk to output valid timing.
13b = Output hold time for non-PCI signals.
14b = SDRAM-SYNC_IN to output high-impedance timing for non-PCI signals.
Tos = Offset timing required to align sys_logic_clk with SDRAM_SYNC_IN. The SDRAM_SYNC_IN signal
sys_logic_clk
VM
PCI_SYNC_IN
VM
is adjusted by the DLL to accommodate for internal delay. This causes SDRAM_SYNC_IN to appear
before sys_logic_clk once the DLL locks.
(after DLL locks)
Shown in 2:1 Mode
Notes:
10b-d = Input signals valid timing.
GVDD_OVDD
10a
11c
PCI_SYNC_IN
PCI
12a
13a
14a
GVDD_OVDD
0.285
Input Timing
Output Timing
Inputs/Outputs
2
GVDD_OVDD
2
GVDD_OVDD
2
0.4 x
GVDD_OVDD x
0.615
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