58
MPC8241 Integrated Processor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
2
—
Section 1.4.1.2—Updated note 1 to include 266-MHz part. Added a line to cautions 2 and 3
in the notes section of Table 2. Added Figures 4 and 5 to show the overshoot and undershoot
requirements for the PCI interface.
Section 1.4.1.3—Table 3: Updated minimum value for input high voltage, and maximum
value for capacitance.
Section 1.4.3.2—Appended Figures 9 and 10.
Section 1.4.3.4—Added a column to Table 13 to include 133-MHz memory bus speed for
266-MHz part.
Section 1.5.2—Changed Figure 24 to accommodate new package offerings.
Section 1.6—Added Table 19 for PLL of the 266-MHz part.
Section 1.7.7—Corrected note numbering in COP connector diagram.
Section 1.9.1—Updated package description in part marking nomenclature.
3
—
Section 1.4.1.2—Changed recommended value in Table 2 for I/O buffer supply to 3.3
± 0.3
V. Changed wording referencing Figure 4 to refer to the MPC8241.
Section 1.4.2—Table 6: Updated values for thermal characterization data as per the new
packaging and 266-MHz part. Added note 7 for the difference between the 166-/200-MHz
and the 266-MHz packaging.
Section 1.4.3—Corrected the voltage listing for the 266-MHz part to 1.8
± 0.1 V in Table 7.
Section 1.5—Changed package parameters and illustration based on new packaging.
Section 1.6—Table 18: Modified PLL configuration for 166- and 200-MHz parts for mode 7
to specify that this mode is not available for Rev. D of the part. Added sentence to note 1
referencing update for mode 7. Table 19: Made several range updates for various modes to
accommodate VCO limits. Added mode 7 and 1E updates for Rev. D. Updated VCO limits
listed in notes 4, 6, and 7.
4
—
Section 1.4.1.2—Table 2: Changed note 1. Figure 2: Updated note 2 and removed ‘voltage
regulator delay’ label since Section 1.7.2 is being deleted this revision. Also, updated Table
5, note 1 to reflect deletion of Section 1.7.2.
Section 1.4.1.3—Table 3: Updated the maximum input capacitance from 15 to 16 pF based
on characterization data.
Section 1.4.3.1—Updated PCI_SYNC_IN jitter specifications to 200 ps.
Section 1.4.3.3—Table 11, item 12b: added the word ‘a(chǎn)ddress’ to help clarify which signals
the spec applies to. Figure 15: edited timing for items 12a0 and 12a2 to correspond with
Table 11.
Section 1.5.2—Changed some dimension values for the side view of package.
Section 1.5.3—Updated notes for the QACK/DA0 signal because this signal has been found
to have no internal pull resistor.
Section 1.6—Updated note numbering list for Table 19. Removed mode 5 from PLL tables
since that mode is no longer supported.
Section 1.7.2 —This section was removed as it was not necessary since the power
information is covered in Section 1.4.1.5.
Section 1.7.4—Added the words ‘the clamping voltage’ to describe LVDD in the sixth
paragraph. Changed the QACK/DA0 signal from the list of signals having an internal pull-up
resistor to the list of signals needing a weak pull-up resistor to OVDD.
Section 1.9.1—Table 21: Added processor version register value column.
5
—
Section 5.1— Updated package information to include all package offerings.
Section 5.2 — Included package case outline for ZP (Rev. B) packaging parts.
Section 9 — Updated Part markings for the offerings of the MPC8241.
All sections — Nontechnical reformatting
Table 20. Revision History Table (continued)
Revision
Date
Substantive Change(s)