- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45354 > MPC8241LZQ266D (MOTOROLA INC) 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 PDF資料下載
參數(shù)資料
| 型號： | MPC8241LZQ266D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357 |
| 文件頁數(shù)： | 44/64頁 |
| 文件大?。?/td> | 827K |
| 代理商： | MPC8241LZQ266D |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當(dāng)前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
49
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
7.5 PCI Reference Voltage—LVDD
The MPC8241 PCI reference voltage (LVDD) pins should be connected to 3.3 ± 0.3 V power supply if
interfacing the MPC8241 into a 3.3-V PCI bus system. Similarly, the LVDD pins should be connected to
5.0 V ± 5% power supply if interfacing the MPC8241 into a 5-V PCI bus system. For either reference
voltage, the MPC8241 always performs 3.3-V signaling as described in the PCI Local Bus Specification
manual (Rev. 2.2). The MPC8241 tolerates 5-V signals when interfaced into a 5-V PCI bus system. (See
Errata No. 18 in the MPC8245/MPC8241 Integrated Processor Chip Errata).
7.6 JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status monitoring
signals. The COP port requires the ability to assert HRESET or TRST independently to control the processor
completely. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, the COP reset signals must be merged into these signals with
logic.
The arrangement shown in Figure 29 allows the COP to assert HRESET or TRST independently while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header are not used,
TRST should be tied to HRESET so that it is asserted when the system reset signal (HRESET) is asserted
to ensure that the JTAG scan chain is initialized during power-on. The COP header shown in Figure 29 adds
many benefits—breakpoints, watchpoints, register and memory examination/modification, and other
standard debugger features are possible through this interface—and can be as inexpensive as an unpopulated
footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a 'Berg header'). The connector typically has
pin 14 removed as a connector key.
Numbering for the COP header shown in Figure 29 is not standardized; consequently, many different pin
numbers have been observed from emulator vendors. Some are numbered top-to-bottom followed by
left-to-right, while others use left-to-right followed by top-to-bottom. Others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 29 is common to all known emulators.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC8241LZP266B | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 |
| MPC8241LZQ166B | 32-BIT, 166 MHz, RISC PROCESSOR, PBGA357 |
| MPC8241LZQ266B | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 |
| MPC8241LVR200B | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA357 |
| MPC8245ARZU400D | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA352 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8241TVR166D | 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8241TVR200D | 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8241TZP166C | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Intergrated Processor Hardware Specifications |
| MPC8241TZP200C | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Intergrated Processor Hardware Specifications |
| MPC8241TZP266C | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Intergrated Processor Hardware Specifications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。