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參數(shù)資料
| 型號： | MPC8240LZU250X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | TBGA-352 |
| 文件頁數(shù)： | 15/52頁 |
| 文件大小： | 542K |
| 代理商： | MPC8240LZU250X |
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22
MPC8240 (rev0.5) Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.3.4 I2C AC Timing Specications
Notes:
1
Units for these specications are in SDRAM_CLK units.
2
The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in
the Frequency Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to
qualied signals. The qualied SCL and SDA are delayed signals from what is seen in real time on the
I2C bus. The qualied SCL, SDA signals are delayed by the SDRAM_CLK clock times DFFSR times 2
plus 1 SDRAM_CLK clock. The resulting delay value is added to the value in the table (where this note is
referenced). See Figure 12.
3
Timing is relative to the Sampling Clock (not SCL).
4
FDR[x] refers to the Frequency Divider Register I2CFDR bit x.
5
Input clock low and high periods in combination with the FDR value in the Frequency Divider Register
Table 12. I2C Input AC Timing Specifications
At recommended operating conditions (See Table 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
4.0
—
CLKs
1,2
2
Clock low period
(The time before the MPC8240 will
drive SCL low as a transmitting slave
after detecting SCL low as driven by
an external master.)
8.0 + (16 x 2FDR[4:2]) x (5 -
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’11) -
2({FDR[5],FDR[1]} == b’00) -
1({FDR[5],FDR[1]} == b’01))
—
CLKs
1,2,4, 5
3
SCL/SDA rise time (from 0.5v to
2.4v)
—1
mS
4
Data hold time
0
—
nS
2
5
SCL/SDA fall time (from 2.4 to 0.5v)
—
1
mS
6
Clock high period
(Time needed to either receive a
data bit or generate a START or
STOP.)
5.0
—
CLKs
1,2, 5
7
Data setup time
3.0
—
ns
3
8
Start condition setup time (for
repeated start condition only)
4.0
—
CLKs
1,2
9
Stop condition setup time
4.0
—
CLKs
1,2
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