參數(shù)資料
型號: MPC755CVT400
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA360
封裝: 25 X 25 MM, 2.77MM HEIGHT, 1.27 MM PITCH, LEAD FREE, PLASTIC, BGA-360
文件頁數(shù): 38/56頁
文件大?。?/td> 1521K
代理商: MPC755CVT400
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
43
System Design Information
Figure 24. JTAG Interface Connection
HRESET
HRESET 6
From Target
Board Sources
HRESET
13
SRESET
NC
11
VDD_SENSE
6
5 1
15
2 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
OVDD
CHKSTP_IN
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
TRST
7
16
2
10
12
(if any)
COP
Header
14 2
Key
QACK
OVDD
10 k
Ω
OVDD
10 k
Ω
OVDD
10 k
Ω
10 k
Ω
QACK
CHKSTP_OUT
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No Pin
COP Connector
Physical Pin Out
10 k
Ω 4
OVDD
1
2 k
Ω 3
0
Ω 5
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC755. Connect
pin 5 of the COP header to OVDD with a 10-kΩ pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-
Ω isolation resistor.
6. The COP port and target board should be able to independently assert HRESET and TRST to the
processor in order to fully control the processor as shown above.
TRST 6
10 k
Ω
OVDD
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