參數(shù)資料
型號(hào)： MPC750PRX400LE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 24/24頁(yè)
文件大?。?/td> 543K
代理商： MPC750PRX400LE
XPC750P RISC Microprocessor Hardware Specications
9
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.2.2 60x Bus Input AC Specications
Table 9. provides the 60x bus input AC timing specications for the XPC750P as dened in Figure 3. and
Figure 4.. Input timing specications for the L2 bus are provided in Section 1.4.2.5, L2 Bus Input AC
Table 9. 60x Bus Input AC Timing Specifications1
At recommended operating conditions (See Table 3.)
Num
Characteristic
300,333,366,400 MHz
Unit
Notes
Min
Max
10a
Address/Data/Transfer Attribute Inputs
Valid to SYSCLK (Input Setup)
2.5
ns
2
10b
All Other Inputs Valid to SYSCLK (Input
Setup)
2.5
ns
3
10c
Mode select input setup to HRESET
(DRTRY, TLBISYNC)
8
t
sysclk
4,5,6,7
11a
SYSCLK to Address/Data/Transfer
Attribute Inputs Invalid (Input Hold)
0
ns
2
11b
SYSCLK to All Other Inputs Invalid (Input
Hold)
0
ns
3
11c
HRESET to mode select input hold
(DRTRY, TLBISYNC)
0
ns
4,6,7
Notes:
1. All input specications are measured from the TTL level (0.8 to 2.0V) of the signal in question
to the 1.4V of the rising edge of the input SYSCLK. Input and output timings are measured at
the pin.
2. Address/Data/Transfer Attribute inputs are composed of the followingA[031], AP[03],
TT[04], TBST, TSIZ[02], GBL, DH[031], DL[031], DP[07].
3. All other signal inputs are composed of the followingTS, ABB, DBB, ARTRY, BG, AACK,
DBG, DBWO, TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK,
TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4.).
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in
the table must be multiplied by the period of SYSCLK to compute the actual time duration (in
nanoseconds) of the parameter in question.
6. Guaranteed by design and characterization.
7. This specication is for conguration mode select only. Also note that the HRESET must be
held asserted for a minimum of 255 bus clocks after the PLL re-lock time during the power-on
reset sequence.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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