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| 型號： | MPC750PRX400LE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 543K |
| 代理商： | MPC750PRX400LE |
8
XPC750P RISC Microprocessor Hardware Specications
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.2.1 Clock AC Specications
Table 8. provides the clock AC timing specications as dened in Figure 2..
Figure 2. provides the SYSCLK input timing diagram.
Figure 2. SYSCLK Input Timing Diagram
Table 8. Clock AC Timing Specifications
At recommended operating conditions (See Table 3.)
Num
Characteristic
300 MHz
333 MHz
366 MHz
400 MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Processor frequency
250
300
250
333
250
366
250
400
MHz
VCO frequency
500
600
500
666
500
733
500
800
MHz
SYSCLK frequency
33
100
33
100
33
100
33
100
MHz
1
SYSCLK cycle time
10
30
10
30
10
30
10
30
ns
2, 3
SYSCLK rise and fall
time
2
ns
2
4
SYSCLK duty cycle
measured at 1.4V
40
60
40
60
40
60
40
60
%
3
SYSCLK jitter
±150
±150
±150
±150
ps
4
Internal PLL relock
time
100
100
100
100
ms5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[03] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to the PLL_CFG[03] signal description in Section 1.8.1,
PLL Conguration, for valid PLL_CFG[03] settings
2. Rise and fall times for the SYSCLK input are measured from 0.4 to 2.4V.
3. Timing is guaranteed by design and characterization.
4. The total input jitter (short term and long term combined) must be under ±150 ps.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable Vdd and SYSCLK are reached during the power-on reset sequence. This
specication also applies when the PLL has been disabled and subsequently re-enabled during sleep mode.
Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time
during the power-on reset sequence.
VM
VM = Midpoint Voltage (1.4V)
2
3
CVIL
CVIH
1
SYSCLK
VM
4
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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