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| 型號： | MPC750ARX266LX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 34/44頁 |
| 文件大小： | 558K |
| 代理商： | MPC750ARX266LX |
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MPC750A RISC Microprocessor Hardware Specications
Features
1.2 Features
This section summarizes features of the MPC750’s implementation of the PowerPC architecture. Major
features of the MPC750 are as follows:
Branch processing unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resolving 2 speculations)
— Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
— 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch
delay slots
Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)
— Dispatch two instructions to six independent units (system, branch, load/store, xed-point unit
1, xed-point unit 2, or oating-point)
— Serialization control (predispatch, postdispatch, execution serialization)
Decode
— Register le access
— Forwarding control
— Partial instruction decode
Load/store unit
— One cycle load or store cache access (byte, half-word, word, double-word)
— Effective address generation
— Hits under misses (one outstanding miss)
— Single-cycle misaligned access within double word boundary
— Alignment, zero padding, sign extend for integer register le
— Floating-point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
— Store gathering
— Cache and TLB instructions
— Big- and little-endian byte addressing supported
— Misaligned little-endian support in hardware
Fixed-point units
— Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shift, rotate, logical
— Multiply and divide support (multi-cycle)
— Early out multiply
Floating-point unit
— Support for IEEE-754 standard single- and double-precision oating-point arithmetic
— 3 cycle latency, 1 cycle throughput, single-precision multiply-add
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