參數(shù)資料
型號(hào)： MPC750ARX200TX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 3.20 MM HIEGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 11/44頁(yè)
文件大?。?/td> 280K
代理商： MPC750ARX200TX
MPC750A RISC Microprocessor Hardware Specications
19
Electrical and Thermal Characteristics
1.4.2.6 L2 Bus Output AC Specications
Table 13 provides the L2 bus output interface AC timing specications for the MPC750 as dened in
Figure 9.
Figure 9 shows the L2 bus output timing diagrams for the MPC750.
Table 13. L2 Bus Output Interface AC Timing Specifications1
At recommended operating conditions (See Table 3), CL = 20 pF3
Num
Characteristic
L2CR[14–15]
Core Freq
200-266MHz
Min
Max
26
L2SYNC_IN to output valid
002
—
5.0
01
—
5.5
10
—
5.7
11
—
6.0
27
L2SYNC_IN to output hold
002
0.5
—
01
1.0
—
10
1.2
—
11
1.5
—
28
L2SYNC_IN to high impedance 002
—
4.0
01
—
4.5
10
—
4.7
11
—
5.0
Notes:
1. All outputs are measured from the midpoint voltage of the rising edge of
L2SYNC_IN to the TTL level (0.8V or 2.0V) of the signal in question. The
output timings are measured at the pins.
2.The outputs are valid for both single-ended and differential L2CLK modes.
For flow-thru and pipelined reg-reg synchronous burst RAMs, L2CR[14–15]
= 00 is recommended. For pipelined delay-write synchronous burst SRAMs,
L2CR[14–15] = 01 is recommended.
3. All maximum timing specifications assume CL =20 pF.
4. This measurement assumes CL = 5 pF.
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