參數(shù)資料
型號: MPC745BPX400LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA255
封裝: 21 X 21 MM, 2.80 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-255
文件頁數(shù): 32/48頁
文件大?。?/td> 1265K
代理商: MPC745BPX400LX
38
MPC755 RISC Microprocessor Hardware Specifications
System Design Information
1.8.7 Pull-up Resistor Requirements
The MPC755 requires high-resistive (weak: 10 k
) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC755 or other bus masters. These pins are TS, ABB, DBB, and ARTRY.
Three test pins also require pull-up resistors (weak or stronger: 4.7 k
–10 k). These pins are
L1_TSTCLK, L2_TSTCLK, and LSSD_MODE. These signals are for factory use only and must be
pulled up to OVdd for normal machine operation.
In addition, the MPC755 has one open-drain style output that requires a pull-up resistor (weak or stronger:
4.7 k
–10 k) if it is used by the system. This pin is CKSTP_OUT.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, float in the high-impedance state for relatively long periods of time. Since the MPC755 must
continually monitor these signals for snooping, this float condition may cause excessive power draw by the
input receivers on the MPC755 or by other receivers in the system. It is recommended that these signals be
pulled up through weak (10 k
) pull-up resistors by the system, or that they may be otherwise driven by the
system during inactive periods of the bus. The snooped address and transfer attribute inputs are: A[0:31],
AP[0:3], TT[0:4], TBST, and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pullups, or that those signals be otherwise driven by the system during inactive periods by the system. The
data bus signals are: DH[0:31], DL[0:31], and DP[0:7].
If 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be disabled,
and their outputs will drive logic zeros when they would otherwise normally be driven. For this mode, these
pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible
output switching.
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity
checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
The L2 interface does not normally require pull-up resistors.
1.8.8 JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the MPC755
are available on the internet at www.mot.com/PowerPC/teksupport.) The TRST signal is optional in the
IEEE 1149.1 specification but is provided on all PowerPC implementations. While it is possible to force the
TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset
performance will be obtained if the TRST signal is asserted during power-on reset. Since the JTAG interface
is also used for accessing the common on-chip processor (COP) function of PowerPC processors, simply
tying TRST to HRESET isn’t practical.
Table 18. Impedance Characteristics
Vdd = 2.0 V, OVdd = 3.3 V, Tj = 0–105°C
Impedance
Processor Bus
L2 Bus
Symbol
Unit
RN
25–36
25-36
Z0
ohms
RP
26
39
26-39
Z0
ohms
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