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參數(shù)資料
| 型號： | MPC7457EC |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 37/68頁 |
| 文件大小： | 1755K |
| 代理商： | MPC7457EC |
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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
37
Pinout Listings
TEA
L1
Low
Input
BVSEL
TEST[0:3]
A12, B6, B10, E10
—
Input
BVSEL
12
TEST[4]
D10
—
Input
BVSEL
9
TMS
F1
High
Input
BVSEL
6
TRST
A5
Low
Input
BVSEL
6, 14
TS
L4
Low
I/O
BVSEL
3
TSIZ[0:2]
G6, F7, E7
High
Output
BVSEL
TT[0:4]
E5, E6, F6, E9, C5
High
I/O
BVSEL
WT
D3
Low
Output
BVSEL
3
V
DD
H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7,
L9, L11, L13, M8, M10, M12
—
—
N/A
Notes:
1.
OV
DD
supplies power to the processor bus, JTAG, and all control signals; and V
DD
supplies power to the processor core
and the PLL (after filtering to become AV
DD
). To program the I/O voltage, connect BVSEL to either GND (selects 1.8 V) or
to HRESET (selects 2.5 V). If used, the pull-down resistor should be less than 250
. For actual recommended value of V
in
or supply voltages see
Table 4
.
Unused address pins must be pulled down to GND.
These pins require weak pull-up resistors (for example, 4.7 k
) to maintain the control signals in the negated state after
they have been actively negated and released by the MPC7447 and other bus masters.
This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
This signal must be negated during reset, by pull up to OV
DD
or negation by HRESET (inverse of HRESET), to ensure
proper operation.
Internal pull up on die.
Ignored in 60x bus mode.
These signals must be pulled down to GND if unused, or if the MPC7447 is in 60x bus mode.
These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10. This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.
11. These signals are for factory use only and must be left unconnected for normal machine operation.
12. These input signals are for factory use only and must be pulled up to OV
DD
for normal machine operation.
13. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
14. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
2.
3.
4.
5.
6.
7.
8.
9.
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package
Signal Name
Pin Number
Active
I/O
I/F Select
1
Notes
A[0:35]
E10, N4, E8, N5, C8, R2, A7, M2, A6, M1, A10, U2,
N2, P8, M8, W4, N6, U6, R5, Y4, P1, P4, R6, M7, N7,
AA3, U4, W2, W1, W3, V4, AA1, D10, J4, G10, D9
High
I/O
BVSEL
2
AACK
U1
Low
Input
BVSEL
AP[0:4]
L5, L6, J1, H2, G5
High
I/O
BVSEL
ARTRY
T2
Low
I/O
BVSEL
3
Table 16. Pinout Listing for the MPC7447, 360 CBGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Select
1
Notes
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MPC745BPX300LE | 功能描述:微處理器 - MPU 255 PBGAREV2.8105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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