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| 型號： | MPC7457EC |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 23/68頁 |
| 文件大小： | 1755K |
| 代理商： | MPC7457EC |
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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
23
Electrical and Thermal Characteristics
5.2.4.1
Effects of L3OHCR Settings on L3 Bus AC Specifications
The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control Register (L3OCHR). Each
field controls the timing for a group of signals. The AC timing specifications presented herein represent the AC
timing when the register contains the default value of 0x0000_0000. Incrementing a field delays the associated
signals, increasing the output valid time and hold time of the affected signals. In the special case of delaying an
L3_CLK signal, the net effect is to decrease the output valid and output hold times of all signals being latched
relative to that clock signal. The amount of delay added is summarized in
Table 12
. Note that these settings affect
output timing parameters only and do not impact input timing parameters of the L3 bus in any way.
Table 11. Sample Points Calculation Parameters
Parameter
Symbol
Max
Unit
Notes
Delay from processor clock to internal_L3_CLK
t
AC
3/4
t
L3_CLK
1
Delay from internal_L3_CLK to L3_CLK[
n
] output pins
t
CO
3
ns
2
Delay from L3_ECHO_CLK[
n
] to receive latch
t
ECI
3
ns
3
Notes
:
1. This specification describes a logical offset between the internal clock edge used to launch the L3 address and control
signals (this clock edge is phase-aligned with the processor clock edge) and the internal clock edge used to launch the
L3_CLK[
n
] signals. With proper board routing, this offset ensures that the L3_CLK[
n
] edge will arrive at the SRAM within a
valid address window and provide adequate setup and hold time. This offset is reflected in the L3 bus interface AC timing
specifications, but must also be separately accounted for in the calculation of sample points and, thus, is specified here.
2. This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding rising or falling
edge at the L3CLK[
n
] pins.
3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[
n
] to data valid and ready to be sampled from
the FIFO.
Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing
At recommended operating conditions. See
Table 4
.
Field Name
1
Affected Signals
Value
Output Valid Time
Output Hold Time
Unit
Notes
Parameter
Symbol
2
Change
3
Parameter
Symbol
2
Change
3
L3AOH
L3_ADDR[18:0],
L3_CNTL[0:1]
0b00
t
L3CHOV
0
t
L3CHOX
0
ps
4
0b01
+50
+50
0b10
+100
+100
0b11
+150
+150
L3CLK
n
_OH
All signals latched by
SRAM connected to
L3_CLK
n
0b000
t
L3CHOV
,
t
L3CHDV
,
t
L3CLDV
0
t
L3CHOX
,
t
L3CHDX
,
t
L3CLDX,
0
ps
4
0b001
– 50
– 50
5
0b010
– 100
– 100
5
0b011
– 150
– 150
5
0b100
– 200
– 200
5
0b101
– 250
– 250
5
0b110
– 300
– 300
5
0b111
– 350
– 350
5
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