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參數(shù)資料
| 型號： | MPC740PRX333LE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 543K |
| 代理商： | MPC740PRX333LE |
16
XPC750P RISC Microprocessor Hardware Specications
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.2.6 L2 Bus Output AC Specications
Table 13. provides the L2 bus output interface AC timing specications for the XPC750P as dened in
Table 13. L2 Bus Output Interface AC Timing Specifications1
At recommended operating conditions (See Table 3.), CL = 20 pF
3
Num
Characteristic
L2CR[1415]
Core Frequency
300-400MHz
Notes
Min
Max
26
L2SYNC_IN to output valid
002
4.2
01
4.7
10
4.9
11
5.2
27
L2SYNC_IN to output hold
002
0.75
4
01
1.25
4
10
1.45
4
11
1.75
4
28
L2SYNC_IN to high
impedance
002
3.5
01
4.0
10
4.2
11
4.5
Notes:
1. All outputs are measured from the midpoint voltage of the rising edge of
L2SYNC_IN to the TTL level (0.8V or 2.0V) of the signal in question. The output
timings are measured at the pins.
2.The outputs are valid for both single-ended and differential L2CLK modes. For
ow-thru and pipelined reg-reg synchronous burst RAMs, L2CR[1415] = 00 is
recommended. For pipelined delay-write synchronous burst SRAMs, L2CR[14
15] = 01 is recommended.
3. All maximum timing specications assume CL =20 pF.
4. This measurement assumes CL = 5 pF.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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