參數(shù)資料
型號: MPC7400RX333TX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 6/44頁
文件大?。?/td> 504K
代理商: MPC7400RX333TX
14
MPC7400 RISC Microprocessor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
1.4.2.2 Processor Bus AC Specications
Table 9 provides the processor bus AC timing specications for the MPC7400 as dened in Figure 4 and
Figure 5. Timing specications for the L2 bus are provided in Section 1.4.2.3, “L2 Clock AC
Table 9. Processor Bus AC Timing Specifications1
At Vdd=AVdd=1.8V±100mV; 0
≤ Tj ≤ 105°C, OVdd = 3.3V±165mV or OVdd = 2.5V±100mV or OVdd=1.8V±100mV
Parameter
Symbol2
350, 400 MHz
Unit
Notes
Min
Max
Mode select input setup to HRESET
tMVRH
8—
t
sysclk
3,4,5,6
HRESET to mode select input hold
tMXRH
0
ns
2,3,5
Setup Times:
Address/Transfer Attribute
Transfer Start (TS)
Data/Data Parity
ARTRY/SHD0/SHD1
All Other Inputs
tAVKH
tTSVKH
tDVKH
tARVKH
tIVKH
1.6
ns
7
8
9
Input Hold Times:
Address/Transfer Attribute
Transfer Start (TS)
Data/Data Parity
ARTRY/SHD0/SHD1
All Other Inputs
tAXKH
tTSXKH
tDXKH
tARXKH
tIXKH
0
ns
7
8
9
Valid Times:
Address/Transfer Attribute
TS, ABB, DBB
Data
Data Parity
ARTRY/SHD0/SHD1
All Other Outputs
tKHAV
tKHTSV
tKHDV
tKHDPV
tKHARV
tKHOV
3.2
3.4
3.5
2.5
3.2
ns
7
8
10
SYSCLK
VM
CVIH
CVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
tKR
tKF
tKHKL
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