參數(shù)資料
型號： MPC7400RX333TX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 333 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù)： 25/44頁
文件大?。?/td> 504K
代理商： MPC7400RX333TX
MPC7400 RISC Microprocessor Hardware Specications
31
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC7400.
1.8.1 PLL Conguration
The MPC7400’s PLL is congured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency,
the PLL conguration signals set the internal CPU and VCO frequency of operation. The PLL conguration
for the MPC7400 is shown in Table 14 for example frequencies.
Table 14. MPC7400 Microprocessor PLL Configuration
PLL_CFG
[0–3]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to
VCO
Multiplier
Bus
25 MHz
Bus
33.3
MHz
Bus
50 MHz
Bus
66.6
MHz
Bus
75 MHz
Bus
100 MHz
0100
2x
0110
2.5x
2x
1000
3x
2x
300 (600)
1110
3.5x
2x
350 (700)
1010
4x
2x
300 (600) 400
(800)
0111
4.5x
2x
300
(600)
337 (675) 450 (900)
1011
5x
2x
333
(666)
375 (750)
1001
5.5x
2x
366
(733)
412
(825)
1101
6x
2x
300 (600) 400
(800)
450 (900)
0101
6.5x
2x
325
(630)
433
(866)
0010
7x
2x
350 (700)
0001
7.5x
2x
375
(750)
1100
8x
2x
400
(800)
0000
9x
2x
300
(600)
450
(900)
0011
PLL off/bypass
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core
implied
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