參數(shù)資料
型號(hào)： MPC603RZT300TA
廠(chǎng)商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, PBGA255
封裝： 23 X 23 MM, 2.60 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-255
文件頁(yè)數(shù)： 12/36頁(yè)
文件大?。?/td> 440K
代理商： MPC603RZT300TA
2
PID7t-603e Hardware Specifications
Overview
This document describes the pertinent physical characteristics of the PID7t-603e from Motorola. For
functional characteristics of the 603e, refer to the PowerPC 603e RISC Microprocessor Users Manual.
This document contains the following topics:
Topic
Page
To locate any published errata or updates for this document, refer to the website at
http://www.motorola.com/semiconductors.
1.1 Overview
This section describes the features of the 603e and describes briey how those units interact.
The 603e is a low-power implementation of the PowerPC microprocessor family of reduced instruction set
computing (RISC) microprocessors. The 603e implements the 32-bit portion of the PowerPC architecture
specication, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and
oating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture
provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit
architecture.
The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and
sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor.
The fourth is a dynamic power management mode that causes the functional units in the 603e to
automatically enter a low-power mode when the functional units are idle without affecting operational
performance, software execution, or any external hardware.
The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock.
Instructions can execute out of order for increased performance; however, the 603e makes completion
appear sequential.
The 603e integrates ve execution unitsan integer unit (IU), a oating-point unit (FPU), a branch
processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute ve
instructions in parallel and the use of simple instructions with rapid execution times yield high efciency
and throughput for 603e-based systems. Most integer instructions execute in one clock cycle. The FPU is
pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
The 603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches
for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs
contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and
ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block
translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The 603e also
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