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    參數(shù)資料
    型號(hào): MPC603RZT300LX
    廠商: MOTOROLA INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, PBGA255
    封裝: 23 X 23 MM, 2.60 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-255
    文件頁(yè)數(shù): 33/36頁(yè)
    文件大?。?/td> 440K
    代理商: MPC603RZT300LX
    6
    PID7t-603e Hardware Specifications
    Electrical and Thermal Characteristics
    Table 4 provides the package thermal characteristics for the PID7t-603e.
    Table 5 provides the DC electrical characteristics for the PID7t-603e.
    Table 4. Package Thermal Characteristics
    Characteristic
    Symbol
    Value
    CBGA
    Value
    PBGA
    Rating
    Package die junction-to-case thermal resistance (typical)
    qJC
    0.095
    8.0
    °C/W
    Package die junction-to-ball thermal resistance (typical)
    qJB
    3.5
    13
    °C/W
    Note: Refer to Section 1.8, “System Design Information,” for more details about thermal management.
    Table 5. DC Electrical Specifications
    Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0
    Tj 105 °C
    Characteristic
    Symbol
    Min
    Max
    Unit
    Notes
    Input high voltage (all inputs except SYSCLK)
    VIH
    2.0
    5.5
    V
    Input low voltage (all inputs except SYSCLK)
    VIL
    GND
    0.8
    V
    SYSCLK input high voltage
    CVIH
    2.4
    5.5
    V
    SYSCLK input low voltage
    CVIL
    GND
    0.4
    V
    Input leakage current, Vin = 3.465 V
    Iin
    30
    A
    1,2
    Vin = 5.5 V
    Iin
    300
    A
    1,2
    Hi-Z (off-state) leakage current, Vin = 3.465 V
    ITSI
    30
    A
    1,2
    Vin = 5.5 V
    ITSI
    300
    A
    1,2
    Output high voltage, IOH = 7 mA
    VOH
    2.4
    V
    Output low voltage, IOL = 7 mA
    VOL
    0.4
    V
    Capacitance, Vin = 0 V, f = 1 MHz (excludes TS, ABB, DBB, and
    ARTRY)
    Cin
    10.0
    pF
    3
    Capacitance, Vin = 0 V, f = 1 MHz (for TS, ABB, DBB, and ARTRY)Cin
    15.0
    pF
    3
    Notes:
    1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals).
    2. The leakage is measured for nominal OVdd and Vdd or both OVdd and Vdd must vary in the same direction
    (for example, both OVdd and Vdd vary by either +5% or -5%).
    3. Capacitance is periodically sampled rather than 100% tested.
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