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參數(shù)資料
| 型號： | MPC603RZT266TX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA255 |
| 封裝： | 23 X 23 MM, 2.60 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-255 |
| 文件頁數(shù)： | 3/36頁 |
| 文件大?。?/td> | 440K |
| 代理商： | MPC603RZT266TX |
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PID7t-603e Hardware Specifications
11
Electrical and Thermal Characteristics
14b
SYSCLK to output valid (all except TS, ABB,
ARTRY, DBB)
—
9.0
ns
5
15
SYSCLK to output invalid (output hold)
1.0
—
ns
2
16
SYSCLK to output high impedance (all except
ARTRY, ABB, DBB)
—
8.0
ns
17
SYSCLK to ABB, DBB, high impedance after
precharge
—
1.0
tsysclk
4, 6
18
SYSCLK to ARTRY high impedance before
precharge
—
7.5
ns
19
SYSCLK to ARTRY precharge enable
0.2 *
tsysclk
+ 1.0
—
ns
2, 4, 7
20
Maximum delay to ARTRY precharge
—
1.0
tsysclk
4, 7
21
SYSCLK to ARTRY high impedance after
precharge
—
2.0
tsysclk
5,7
Notes:
1. All output specications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V
or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 4).
2. This minimum parameter assumes CL = 0 pF.
3. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external
voltage from 5.5 V to 0.8 V instead of from Vdd to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels).
4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the
table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of
the parameter in question.
5. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V.
6. Nominal precharge width for ABB and DBB is 0.5 tsysclk.
7. Nominal precharge width for ARTRY is 1.0 tsysclk.
Table 9. Output AC Timing Specifications1 (Continued)
Vdd = AVdd = 2.5
± 5% V dc, OVdd = 3.3 ± 5%, GND = 0 V dc, 0 Tj 105 °C, CL = 50 pF (unless otherwise noted)
Num
Characteristic
200, 266, 300 MHz
Unit
Notes
Min
Max
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