參數(shù)資料
型號： MPC5602PEF0VLL4
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-100
文件頁數(shù)： 9/95頁
文件大?。?/td> 1694K
代理商： MPC5602PEF0VLL4
MPC5602P Microcontroller Data Sheet, Rev. 4.1
Freescale Semiconductor
17
Counters can share available input pins
Count once or repeatedly
Pins available as GPIO when timer functionality not in use
1.5.26
Analog-to-digital converter (ADC) module
The ADC module provides the following features:
Analog part:
1 on-chip analog-to-digital converter
— 10-bit AD resolution
— 1 sample and hold unit
— Conversion time, including sampling time, less than 1 s (at full precision)
— Typical sampling time is 150 ns minimum (at full precision)
— DNL/INL ±1 LSB
—TUE < 1.5 LSB
— Single-ended input signal up to 3.3 V/5.0 V
— 3.3 V/5.0 V input reference voltage
— ADC and its reference can be supplied with a voltage independent from VDDIO
— ADC supply can be equal or higher than VDDIO
— ADC supply and ADC reference are not independent from each other (both internally bonded to same pad)
— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
Digital part:
16 input channels
4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in
the appropriate ADC result location
2 modes of operation: Motor Control mode or Regular mode
Regular mode features
— Register based interface with the CPU: control register, status register and 1 result register per channel
— ADC state machine managing 3 request flows: regular command, hardware injected command and software
injected command
— Selectable priority between software and hardware injected commands
— DMA compatible interface
CTU-controlled mode features
— Triggered mode only
— 4 independent result queues (1×16 entries, 2×8 entries, 1×4 entries)
— Result alignment circuitry (left justified and right justified)
— 32-bit read mode allows to have channel ID on one of the 16-bit part
— DMA compatible interfaces
1.5.27
Cross triggering unit (CTU)
The cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU
load during the PWM period and with minimized CPU load for dynamic configuration.
It implements the following features:
Double buffered trigger generation unit with up to 8 independent triggers generated from external triggers
相關(guān)PDF資料
PDF描述
MPC5601PEF0MLL4R 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100
MPC5602PEF0VLH6R 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP64
MPC5601F0MLL6R 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100
MPC5602F0MLH6R 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP64
MPC5602F0MLL4 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC5602PEF0VLL4R 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC5602P Microcontroller Data Sheet
MPC5602PEF0VLL6R 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC5602P Microcontroller Data Sheet
MPC5602S 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC5606S Microcontroller Data Sheet
MPC5603B 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Qorivva MPC560xB/C/D Family
MPC5603BEMLL 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC5604B/C Microcontroller Data Sheet
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