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參數(shù)資料
| 型號： | MPC5602DF1CLL4 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-100 |
| 文件頁數(shù)： | 60/83頁 |
| 文件大小： | 1473K |
| 代理商： | MPC5602DF1CLL4 |
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Electrical characteristics
MPC5602D Microcontroller Data Sheet, Rev. 4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
63
4.18.2
DSPI characteristics
3 During the conversion, the total current consumption is given from the sum of the static and dynamic
consumption, i.e., (41 + 5) * fperiph.
Table 43. DSPI characteristics1
1 Operating conditions: C
OUT = 10 to 50 pF, Slew
IN = 3.5 to 15 ns
No.
Symbol
C
Parameter
DSPI0/DSPI1
Unit
Min
Typ
Max
1tSCK
SR
D SCK cycle time
Master mode
(MTFE = 0)
125
—
ns
D
Slave mode
(MTFE = 0)
125
—
D
Master mode
(MTFE = 1)
83
—
D
Slave mode
(MTFE = 1)
83
—
—fDSPI
SR
D DSPI digital controller frequency
—
fCPU
MHz
—
t
CSC
CC
D Internal delay between pad
associated to SCK and pad
associated to CSn in master
mode
Master mode
—
1302
2 Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad
ns
—
t
ASC
CC
D Internal delay between pad
associated to SCK and pad
associated to CSn in master
mode for CSn1
1
Master mode
—
ns
2tCSCext
3
SR
D CS to SCK delay
Slave mode
32
—
ns
3tASCext
4
SR
D After SCK delay
Slave mode
1/fDSPI + 5
—
ns
4tSDC
CC
D SCK duty cycle
Master mode
—
tSCK/2
—
ns
SR
D
Slave mode
tSCK/2
—
5tA
SR
D Slave access time
—
1/fDSPI +70
—
ns
6tDI
SR
D Slave SOUT disable time
—
7
—
ns
9tSUI
SR
D Data setup time for inputs
Master mode
43
—
ns
Slave mode
5
—
10
tHI
SR
D Data hold time for inputs
Master mode
0
—
ns
Slave mode
25
——
11
tSUO
6
CC
D Data valid after SCK edge
Master mode
—
32
ns
Slave mode
—
52
12
tHO
CC
D Data hold time for outputs
Master mode
0
—
ns
Slave mode
8
—
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