參數(shù)資料
型號: MPC5601PEF0MLL4R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-100
文件頁數(shù): 65/95頁
文件大小: 1694K
代理商: MPC5601PEF0MLL4R
MPC5602P Microcontroller Data Sheet, Rev. 4.1
Freescale Semiconductor
68
Table 35. RESET electrical characteristics
Symbol
C
Parameter
Conditions1
1 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Value2
2 All values need to be confirmed during device validation.
Unit
Min
Typ
Max
VIH
SR P Input high level CMOS
(Schmitt Trigger)
0.65VDD
—VDD +0.4 V
VIL
SR P Input low level CMOS
(Schmitt Trigger)
0.4
0.35VDD
V
VHYS CC C Input hysteresis CMOS
(Schmitt Trigger)
—0.1VDD
——
V
VOL
CC P Output low level
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.1VDD
V
Push Pull, IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 13
3 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
device reference manual).
0.1VDD
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
——
0.5
ttr
CC D Output transition time
output pin4 MEDIUM
configuration
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
10
ns
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
20
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
40
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
12
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
25
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
40
WFRST SR P RESET input filtered
pulse
——
40
ns
WNFRST SR P RESET input not filtered
pulse
500
ns
tPOR CC D Maximum delay before
internal reset is released
after all VDD_HV reach
nominal supply
Monotonic VDD_HV supply ramp
1
ms
|IWPU| CC P Weak pull-up current
absolute value
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
150
A
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
150
VDD = 5.0 V ± 10%, PAD3V5V = 15
10
250
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