參數(shù)資料
型號(hào)： MPC5601F0MLH6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁(yè)數(shù)： 51/95頁(yè)
文件大?。?/td> 1694K
代理商： MPC5601F0MLH6
MPC5602P Microcontroller Data Sheet, Rev. 4.1
Freescale Semiconductor
55
tCYC
D System clock period
—
1 / fSYS
ns
fLORL
D Loss of reference frequency window3
Lower limit
1.6
3.7
MHz
fLORH
D
Upper limit
24
56
fSCM
D Self-clocked mode frequency4,5
—
20
150
MHz
CJITTER
T CLKOUT period
jitter6,7,8,9
Short-term jitter10
fSYS maximum
44
% fCLKOUT
Long-term jitter
(average over 2 ms
interval)
fPLLIN =16MHz
(resonator), fPLLCLK at
64 MHz, 4000 cycles
—10
ns
tlpll
D PLL lock time11, 12
—
200
s
tdc
D Duty cycle of reference
—
40
60
%
fLCK
D Frequency LOCK range
—
66
% fSYS
fUL
D Frequency un-LOCK range
—
18
% fSYS
fCS
D Modulation depth
Center spread
±0.25
±4.013
%fSYS
fDS
D
Down spread
0.5
8.0
fMOD
D Modulation frequency14
—
70
kHz
1 VDD_LV_CORx = 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified
2 Considering operation with PLL not bypassed.
3 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked
mode.
4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside
the fLOR window.
5 fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
6 This value is determined by the crystal manufacturer and board design.
7 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDD_LV_COR0 and VSS_LV_COR0 and variation in crystal oscillator
frequency increase the CJITTER percentage for a given interval.
8 Proper PC board layout procedures must be followed to achieve specifications.
9 Values are obtained with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of
CJITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
10 Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
11 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this PLL, load capacitors should not exceed these limits.
12 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
13 This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
14 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
Table 26. FMPLL electrical characteristics (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Max
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MPC5601PEF0MLH4R 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:MPC5602P Microcontroller Data Sheet
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