參數(shù)資料
型號： MPC5561MZQ80
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： FLASH, 80 MHz, MICROCONTROLLER, PBGA324
封裝： 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, TEPBGA-324
文件頁數(shù)： 42/56頁
文件大?。?/td> 1044K
代理商： MPC5561MZQ80
Revision History for the MPC5561 Data Sheet
MPC5561 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
47
5
Revision History for the MPC5561 Data Sheet
The history of revisions made to this data sheet are shown in this section. The changes are divided into
each revision of this document. The substantive changes incorporated in MPC5561 Data Sheet Rev. 0.0 to
produce Rev. 1.0 of this document are grouped as follows:
Global and text changes
Table and figure changes
Within each group, the changes are listed in sequential order.
5.1
Information Changed Between Revisions 0.0 and 1.0
The following table lists the global changes made throughout the document, as well as substantive changes
to text that is not in a table of figure.
Table 27. Global and Text Changes Between Rev. 0.0 and Rev. 1.0
Location
Description of Changes
Global Changes throughout the document
Replaced kilobytes with KB.
Replaced megabytes with MB.
First paragraph: text changed from “. . . based on the PowerPC Book E architecture” to “. . . built on the Power
Architecture embedded technology.”
Second paragraph: Changed terminology from PowerPC Book E architecture to Power Architecture terminology.
Added new third paragraph about VLE feature.
Added new eighth paragraph about the parallel digital interface (PDI).
Paragraph nine: changed “the MPC5561 has an on-chip 20-channel enhanced queued analog-to-digital
converter (eQADC)” to “. . . has an on-chip 40-channel dual enhanced queued . . .”
Added the sentence preceding Table 1: ‘Unless noted in this data sheet, all specifications apply from TL to TH.’
Sections 3.7.1, 3.7.2 and 3.7.3: Reordered sections resulting in the following order and section renumbering:
From: ‘To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as ones
(1s) when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6) when powering the device
by more than the VDD33 lag specification in Table 6. VDD33 individually can lag either VDDSYN or the RESET power
pin (VDDEH6) by more than the VDD33 lag specification. VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but
cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification only applies during power up.
VDD33 has no lead or lag requirements when powering down.’
To:
‘When powering the device, VDD33 must not lag VDDSYN and the RESET power pin (VDDEH6) by more than the
VDD33 lag specification listed in Table 6. This avoids accidentally selecting the bypass clock mode because the
internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when
POR negates. VDD33 can lag VDDSYN or the RESET power pin (VDDEH6), but cannot lag both by more than the
VDD33 lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag
requirements when powering down.’
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