參數(shù)資料
型號: MPC5553MZP132
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 132 MHz, MICROCONTROLLER, PBGA416
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-416
文件頁數(shù): 32/68頁
文件大?。?/td> 1261K
代理商: MPC5553MZP132
MPC5553 Microcontroller Data Sheet, Rev. 3.0
Electrical Characteristics
Freescale Semiconductor
38
3.13.7
eMIOS Timing
Figure 17. eMIOS Timing
3.13.8
DSPI Timing
Table 25. eMIOS Timing 1
1 eMIOS timing specified at: V
DDEH = 3.0–5.25 V and TA = TL to TH.
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
eMIOS input pulse width
tMIPW
4—
tCYC
2
eMIOS output pulse width
tMOPW
1 2
2 This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR).
—tCYC
Table 26. DSPI Timing12
Spec
Characteristic
Symbol
80 MHz
112 MHz
132 MHz
Unit
Min.
Max.
Min.
Max.
Min.
Max.
1
SCK cycle time3, 4
tSCK
24.4 ns
2.9 ms
17.5 ns
2.1 ms
15.2 ns
1.7 ms
2
PCS to SCK delay5
tCSC
23
15
13
ns
3
After SCK delay6
tASC
22
14
12
ns
4
SCK duty cycle
tSDC
(tSCK ÷ 2)
– 2 ns
(tSCK ÷ 2)
+ 2 ns
(tSCK ÷ 2)
– 2 ns
(tSCK ÷ 2)
+ 2 ns
(tSCK ÷ 2)
– 2 ns
(tSCK ÷ 2)
+ 2 ns
ns
5
Slave access time
(SS active to SOUT driven)
tA
25
25
25
ns
6
Slave SOUT disable time
(SS inactive to SOUT Hi-Z, or invalid)
tDIS
25
25
25
ns
7PCSx to PCSS time
tPCSC
4—
4
4
ns
8PCSS to PCSx time
tPASC
5—
5
5
ns
1
2
eMIOS
output
eMIOS input
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC551x
and
MPC5533
products
in
208
MAPBGA
packages;
MPC5534
and
MPC5553
products
in
208
and
496
MAPBGA
packages;
MPC5554,
MPC5565,
MPC5566
and
MPC5567
products
in
496
MAPBGA
packages
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