Revision History for the MPC5553 Data Sheet
MPC5553 Microcontroller Data Sheet, Rev. 3.0
Freescale Semiconductor
65
Table 17 Pad AC Specifications and
Table 18 Derated Pad AC Specifications: The changes are identical in the tables.
Table 17 Pad AC Specifications ONLY: Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’ Footnote 1, deleted ‘FSYS =132 MHz.’
Footnote 2, changed from ‘tested’ to ‘(not tested).’
Footnote 3, changed from ‘Out delay’ to ‘The output delay’,
Changed from ‘Add a maximum of one system clock to the output delay to get the output delay with respect to
the system clock‘ to ‘To calculate the output delay with respect to the system clock, add a maximum of one system
clock to the output delay.’
Footnote 4: changed ‘Delay’ to ‘The output delay.’
Footnote 5: deleted ‘before qualification.’ Changed from ‘This parameter is supplied for reference and is not
guaranteed by design and not tested’ to ‘This parameter is supplied for reference and is guaranteed by design
and tested.’
Changed from ‘This parameter is supplied for reference and is not guaranteed by design and not tested’ to ‘This
parameter is supplied for reference and is guaranteed by design and tested.’
Table 19 Reset and Configuration Pin Timing: Footnote 1, deleted ‘FSYS = 132 MHz.’ Table 20 JTAG Pin AC Electrical Characteristics:
Footnote 1, deleted: ‘ and CL = 30 pF with DSC = 0b10, SRC = 0b11,’ changed ‘functional’ to ‘Nexus.’
Changed Spec 12, TCK Low to TDO Data Valid: Changed ‘VDDE = 3.0 to 3.6 volts’ maximum value in column 4
from 9 to 10. Now reads ‘VDDE = 3.0–3.6 V’ with a max value of 10.
External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum
frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow
for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM, and 132 MHz parts allow for 128 MHz system clock +
2% FM.
Spec 1: Changed the values in Min. columns: 40 MHz from 25 to 24.4; 56 MHz from 17.9 to 17.5
Specs 7 and 8: Removed from external bus interface: BDIP, OE, WE/BE[0:1]; removed from the calibration bus
interface CAL_CS[0, 2:3], CAL_WE/BE[0:1].
Deleted duplicate footnote: The EBTS = 0 timings are tested and valid at VDDE = 2.25–3.6 V only, whereas
EBTS = 1 timings are tested and valid at VDDE = 1.6–3.6 V.
Added a footnote each for the DATA[0:31], TEA, and WE/BE[0:3] signals in the table: Due to pin limitations, the
DATA[16:31], TEA, and WE/BE[2:3] signals are not available on the 324 package.
Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Footnote 1: Deleted ‘FSYS = 132 MHz.’, ‘VDD = 1.35–1.65 V’, ‘VDD33 and VDDSYN = 3.0–3.6 V.’ and
‘ and CL = 200 pF with SRC = 0b11.’
Deleted second figure after table ‘External Interrupt Setup Timing.’
Table 24 eTPU Timing
Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Footnote 1: Deleted ‘FSYS = 132 MHz.’, ‘VDD = 1.35–1.65 V’,‘VDD33 and VDDSYN = 3.0–3.6’ and
‘ and CL = 200 pF with SRC = 0b11.’
Deleted second figure, ‘eTPU Input/Output Timing’ after this table.
Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Table 33. Table and Figure Changes Between Rev. 2.0 and 3.0 (continued)
Location
Description of Changes
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC551x
and
MPC5533
products
in
208
MAPBGA
packages;
MPC5534
and
MPC5553
products
in
208
and
496
MAPBGA
packages;
MPC5554,
MPC5565,
MPC5566
and
MPC5567
products
in
496
MAPBGA
packages