參數(shù)資料
型號(hào)： MPC5553MVF132
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 132 MHz, MICROCONTROLLER, PBGA208
封裝： 17 X 17 MM, 1 MM PITCH, MO-151AAF-1, MAPBGA-208
文件頁數(shù)： 63/68頁
文件大?。?/td> 1261K
代理商： MPC5553MVF132
MPC5553 Microcontroller Data Sheet, Rev. 3.0
Revision History for the MPC5553 Data Sheet
Freescale Semiconductor
66
Table 25 eMIOS Timing:
Deleted (MTS) from the heading, table, and footnotes.
Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Footnote 1: Deleted ‘FSYS = 132 MHz’, ‘VDD = 1.35–1.65 V’, ‘VDD33 and VDDSYN = 3.0–3.6 V’ and
‘ and CL = 200 pF with SRC = 0b11.’
Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Figure 17 Added eMIOS Timing figure.
Table 26 DSPI Timing:
Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM, and 132 MHz parts allow for 128 MHz system clock +
2% FM.
Spec 1: SCK cycle time; Changed 80 MHz = 24.4, and 112 MHz = 17.5.
Footnote 1: Changed to read: ‘All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type
M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate.’ Deleted
‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6 V.
Table 27 EQADC SSI Timing Characteristics:
Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Deleted from table title ‘(Pads at 3.3 V or 5.0 V)’
Deleted 1st line in table ‘CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.’
Spec 1: FCK frequency -- removed.
Combined footnotes 1 and 2, and moved the new footnote to Spec 2. Moved old footnote 3 that is now
footnote 2 to Spec 2.
Footnote 1, deleted ‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6V.’
Changed ‘CL = 50 pF’ to ‘CL = 25 pF.’
Footnote 2: added ‘cycle’ after ‘duty’ to read: FCK duty cycle is not 50% when . . . .
Removed the ‘M’ in the diagram labels that refer to the specification numbers.
Figure 32 MPC5553 208 Package: Deleted the version number and date.
Figure 33 MPC5553 324 Package: Deleted the version number and date.
Figure 34 and Figure 35 MPC5553 416 Package: Deleted the version number and date.
Table 33. Table and Figure Changes Between Rev. 2.0 and 3.0 (continued)
Location
Description of Changes
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC551x
and
MPC5533
products
in
208
MAPBGA
packages;
MPC5534
and
MPC5553
products
in
208
and
496
MAPBGA
packages;
MPC5554,
MPC5565,
MPC5566
and
MPC5567
products
in
496
MAPBGA
packages
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