參數(shù)資料
型號(hào): MPC5200VR400BR2
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 25/72頁(yè)
文件大?。?/td> 0K
描述: IC MPU 32BIT 400MHZ 272-PBGA
標(biāo)準(zhǔn)包裝: 500
系列: MPC52xx
核心處理器: e300
芯體尺寸: 32-位
速度: 400MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,J1850,SPI,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲(chǔ)器類(lèi)型: 外部程序存儲(chǔ)器
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.42 V ~ 1.58 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 272-BBGA
包裝: 帶卷 (TR)
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
31
Figure 15. Multiword DMA Timing
NOTE
The direction of signal assertion is towards the top of the page, and the direction of negation
is towards the bottom of the page, irrespective of the electrical properties of the signal.
Table 29. Ultra DMA Timing Specification
Sym
MODE 0
(ns)
MODE 1
(ns)
MODE 2
(ns)
Comment
SpecID
Min
Max
Min
Max
Min
Max
tCYC
114
75
55
Cycle time allowing for asymmetry and clock
variations from STROBE edge to STROBE edge
A8.26
t 2CYC
235
156
117
Two-cycle time allowing for clock variations, from
rising edge to next rising edge or from falling edge to
next falling edge of STROBE.
A8.27
t DS
15
10
7
Data setup time at recipient.
A8.28
t DH
5—5—5—
Data hold time at recipient.
A8.29
t DVS
70
48
34
Data valid setup time at sender, to STROBE edge.
A8.30
t DVH
6
6
6
Data valid hold time at sender, from STROBE edge.
A8.31
t FS
0
230
0
200
0
170
First STROBE time for drive to first negate DSTROBE
from STOP during a data-in burst.
A8.32
t LI
015001500150
Limited Interlock time.
A8.33
t MLI
20
20
20
Interlock time with minimum.
A8.34
t UI
0—0—0—
Unlimited interlock time.
A8.35
t0
tC
tE
tI
tD
tF
tH
tG
tJ
DMARQ
RDATA
WDATA
(Drive)
(Host)
(Drive)
(Host)
tL
tK
DMACK
DIOR
DIOW
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