參數(shù)資料
型號: MPC5200CBV266R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 266 MHz, MICROPROCESSOR, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272
文件頁數(shù): 24/80頁
文件大?。?/td> 6728K
代理商: MPC5200CBV266R2
MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
30
3.3.7.2
Burst Mode
Table 25. Burst Mode Timing
NOTES:
1. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified 0 - 65535.
2. Example:
Long Burst is used, this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a
burst on the internal XLB is executed. => LB = 1
Data bus width is 8 bit. => DS = 8
=> 41*2*(32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line.
Wait State is set to 10. => WS = 10
1+10+32 = 43 => CS is asserted for 43 PCI cycles.
3. ACK is output and indicates the burst.
Sym
Description
Min
Max
Units Notes SpecID
tCSA
PCI CLK to CS assertion
-
1.8
ns
A7.20
tCSN
PCI CLK to CS negation
-
1.8
ns
A7.21
t1
CS pulse width
(1+WS+4LB*2*(32/DS))*
tPCIck
(1+WS+4LB*2*(32/DS))
*tPCIck
ns
1,2
A7.22
t2
ADDR valid before CS assertion
tIPBIck
tPCIck
ns
A7.23
t3
ADDR hold after CS negation
-
-0.7
ns
A7.24
t4
OE assertion before CS assertion
-
0.4
ns
A7.25
t5
OE negation before CS negation
-
0.4
ns
A7.26
t6
RW valid before CS assertion
tPCIck
-
ns
A7.27
t7
RW hold after CS negation
tPCIck
-
ns
A7.28
t8
DATA setup before rising edge of
PCI
1.8
-
ns
A7.29
t9
DATA hold after rising edge of PCI
0
-
ns
A7.30
t10
DATA hold after CS negation
0
(DC+1)*tPCIck
ns
A7.31
t11
ACK assertion after CS assertion
-
(WS+1)*tPCIck
ns
A7.32
t12
ACK negation before CS negation
-
0.6
ns
3
A7.33
t13
ACK pulse width
4LB*2*(32/DS)*tPCIck
ns
2,3
A7.34
t14
CS assertion after TS assertion
-
0.8
ns
A7.35
t15
TS pulse width
tPCIck
ns
A7.36
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