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參數(shù)資料
| 型號(hào)： | MPC5125YVN400 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 400 MHz, MICROCONTROLLER, PBGA324 |
| 封裝： | 23 X 23 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-034AJJ-1, TEPBGA-324 |
| 文件頁數(shù)： | 51/92頁 |
| 文件大?。?/td> | 640K |
| 代理商： | MPC5125YVN400 |
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Electrical and Thermal Characteristics
MPC5125 Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
55
4.3.6
LPC
The local-plus bus is the external bus interface of the MPC5125. A maximum of eight configurable chip selects (CS) are
provided. There are two main modes of operation: non-MUXed and MUXed. The reference clock is the LPC CLK. The
maximum bus frequency is 66 MHz.
Definition of terms:
WS = Wait state
DC = Dead cycle
HC = Hold cycle
DS = Data size in bytes
BBT =Burst bytes per transfer
AL = Address latch enable length
ALT = Chip select/Address Latch Timing
tLPCck = LPC clock period
Table 25. LPC Timing
Sym
Description
Min
Max
Units
SpecID
tOD CS[x], ADDR, R/W, TSIZ, DATA (wr), TS,
OE valid after LPC CLK
(Output delay related to LPC CLK)
05
ns
A7.1
t1 Non-burst CS[x] pulse width
(2 + WS)
× t
LPCck
(2 + WS)
× t
LPCck
ns
A7.2
t2 ADDR, R/W, TSIZ, DATA (wr) valid before
CS[x] assertion
tLPCck tOD
tLPCck + tOD
ns
A7.3
t3
OE assertion after CS[x] assertion
tLPCck tOD
tLPCck + tOD
ns
A7.4
t4 ADDR, R/W, TSIZ, data (wr) hold after
CS[x] negation
tLPCck tOD
(HC + 1)
× t
LPCck + tOD
ns
A7.5
t5
TS pulse width
tLPCck
ns
A7.6
t6 DATA (rd) setup before LPC CLK
5
—
ns
A7.7
t7 DATA (rd) input hold
0
(DC + 1)
× t
LPCck
ns
A7.8
t8
Read burst CS[x] pulse width
(2 + WS + BBT/DS)
× t
LPCck
(2 +WS + BBT/DS)
× t
LPCck
ns
A7.9
t9 Burst ACK pulse width
(BBT/DS)
× t
LPCck
(BBT/DS)
× t
LPCck
ns
A7.10
t10 Burst DATA (rd) input hold
0
—
ns
A7.11
t11 Read burst ACK assertion after CS[x] assertion
(2+WS)
× t
LPCck
(2+WS)
× t
LPCck
ns
A7.12
t12 Non-MUXed write burst CS[x] pulse width
(2.5 + WS + BBT/DS)
× t
LPCck (2.5 + WS + BBT/DS) × tLPCck
ns
A7.13
t13 Write burst ADDR, R/W, TSIZ, DATA (wr)
hold after CS[x] negation
0.5
× t
LPCck – tOD
(HC + 0.5)
× t
LPCck + tOD
ns
A7.14
t14 Write burst ACK assertion after CS[x] assertion
(2.5 + WS)
× t
LPCck – tOD
(2.5 + WS)
× t
LPCck + tOD
ns
A7.15
t15 Write burst DATA valid
tLPCck – tOD
—
ns
A7.16
t16 Non-MUXed mode: asynchronous write
burst ADDR valid before write DATA valid
0.5
× t
LPCck – tOD
0.5
× t
LPCck + tOD
ns
A7.17
t17 MUXed mode: ADDR cycle
AL
× 2 × t
LPCck – tOD
AL
× 2 × t
LPCck
ns
A7.18
t18 MUXed mode: ALE cycle
AL
× t
LPCck
AL
× t
LPCck
ns
A7.19
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