參數(shù)資料
型號： MPC5125YVN400
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 400 MHz, MICROCONTROLLER, PBGA324
封裝： 23 X 23 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-034AJJ-1, TEPBGA-324
文件頁數(shù)： 47/92頁
文件大小： 640K
代理商： MPC5125YVN400
Electrical and Thermal Characteristics
MPC5125 Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
51
4.3.5.1
DDR SDRAM AC Timing Specifications
4.3.5.2
MobileDDR/LPDDR SDRAM AC Timing Specifications
Table 21. DDR SDRAM Timing Specifications
At recommended operating conditions with VDD_IO_MEM of ±5%
Parameter
Symbol
Min
Max
Unit Notes SpecID
Clock cycle time, CL = x
tCK
6000
—
ps
A5.1
MCK AC differential crosspoint voltage
VOX-AC (VDD_IO_MEM × 0.5)– 0.15 (VDD_IO_MEM × 0.5) + 0.15
V
1
NOTES:
1 Measured with clock pin loaded with differential 100
Ω termination resistor.
A5.2
CK HIGH pulse width
tCH
0.47
0.53
tCK
A5.3
CK LOW pulse width
tCL
0.47
0.53
tCK
A5.4
Skew between MCK and DQS transitions
tDQSS
0.25
tCK
2,3
2 Measured with all outputs except the clock loaded with 50
Ω termination resistor to V
DD_IO_MEM/2.
3 All transitions measured at mid-supply (V
DD_IO_MEM/2).
A5.5
Address and control output setup time
relative to MCK rising edge
tOS(base)
tCK/2 – 1000
—
ps
A5.6
Address and control output hold time
relative to MCK rising edge
tOH(base)
tCK/2 – 1000
—
ps
A5.7
DQ and DM output setup time relative to
DQS
tDS1(base)
tCK/4 – 750
—
ps
A5.8
DQ and DM output hold time relative to
DQS
tDH1(base)
tCK/4 – 750
—
ps
A5.9
DQS-DQ skew for DQS and associated
DQ inputs
tDQSQ
– (tCK/4 – 600)
tCK/4 – 600
ps
A5.10
DQS window position related to CAS read
command
tDQSEN
2tCK + 1500
3tCK – 1000
ps 1,2,3,4,
5
4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low.
5 The window position is given for t
DQSEN = 2.0 tCK (RDLY = 2, HALF DQS DLY = QUART DQS DLY = 0) with CL = 3 DDR
SDRAM device. For other values of tDQSEN, the window position is shifted accordingly.
A5.11
Table 22. MobileDDR/LPDDR SDRAM Timing Specifications
At recommended operating conditions with VDD_IO_MEM of ±5%
Parameter
Symbol
Min
Max
Unit Notes SpecID
Clock cycle time, CL = x
tCK
6000
—
ps
A5.1
MCK AC differential crosspoint voltage
VOX-AC (VDD_IO_MEM × 0.5) – 0.1 (VDD_IO_MEM × 0.5) + 0.1
V
1
A5.2
CK HIGH pulse width
tCH
0.47
0.53
tCK
A5.3
CK LOW pulse width
tCL
0.47
0.53
tCK
A5.4
Skew between MCK and DQS
transitions
tDQSS
0.25
tCK
2,3
A5.5
Address and control output setup time
relative to MCK rising edge
tOS(base)
tCK/2 – 1000
—
ps
A5.6
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