參數(shù)資料
型號: MPC5123VY400BR
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA516
封裝: 27 X 27 MM, ROHS COMPLIANT, PLASTIC, TFBGA-516
文件頁數(shù): 76/86頁
文件大?。?/td> 1266K
代理商: MPC5123VY400BR
MPC5121E/MPC5123 Data Sheet, Rev. 1
System Design Information
Freescale Semiconductor
78
4.5.1.1
TRST and PORESET
The JTAG interface can control the direction of the MPC5121e/MPC5123 I/O pads via the boundary scan chain. The JTAG
module must be reset before the MPC5121e/MPC5123 comes out of power-on reset; do this by asserting TRST before
PORESET is released.
For more details refer to the Reset and JTAG Timing Specification.
Figure 60. PORESET vs. TRST
4.5.2
e300 COP/BDM Interface
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
4.5.2.1
Boards Interfacing the JTAG Port via a COP Connector
The MPC5121e/MPC5123 functional pin interface and internal logic provides access to the embedded e300 processor core
through the Freescale standard COP/BDM interface. Table 52 gives the COP/BDM interface signals. The pin order shown
reflects only the COP/BDM connector order.
Table 52. COP/BDM Interface Signals
BDM
Pin #
MPC5121e/MPC51
23 I/O Pin
BDM Connector
Internal
Pull Up/Down
External
Pull Up/Down
I/O1
16
GND
15
CKSTP_OUT
ckstp_out
10k Pull-Up
I
14
KEY
13
HRESET
hreset
Pull-Up
10k Pull-Up
O
12
GND
11
SRESET
sreset
Pull-Up
10k Pull-Up
O
10
N/C
9
TMS
tms
Pull-Up
10k Pull-Up
O
8
CKSTP_IN
ckstp_in
10k Pull-Up
O
7
TCK
tck
Pull-Up
10k Pull-Up
O
6—
VDD2
——
5See Note3
halted3
——
I
4TRST
trst
Pull-Up
10k Pull-Up
O
3
TDI
tdi
Pull-Up
10k Pull-Up
O
TRST
PORESET
Required assertion of TRST
Optional assertion of TRST
Preliminary
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