參數(shù)資料
型號： MPC5123VY400BR
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, ROHS COMPLIANT, PLASTIC, TFBGA-516
文件頁數(shù)： 25/86頁
文件大小： 1266K
代理商： MPC5123VY400BR
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 1
Freescale Semiconductor
31
3.3.4
External Interrupts
The MPC5121e/MPC5123 provides three different kinds of external interrupts:
IRQ interrupts
GPIO interrupts with simple interrupt capability (not available in power-down mode)
WakeUp interrupts
IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge triggered mode.
3.3.5
SDRAM (DDR)
The MPC5121e/MPC5123 memory controller supports three types of DDR devices:
DDR-1 (SSTL_2 class II interface)
DDR-2 (SSTL_18 interface)
LPDDR/Mobile-DDR (1.8V I/O supply voltage)
JEDEC standards define the minimum set of requirements for complient memory devices:
— JEDEC STANDARD, DDR2 SDRAM SPECIFICATION, JESD79-2C, MAY 2006
— JEDEC STANDARD, Double Data Rate (DDR) SDRAM Specification, JESD79E, May 2005
— JEDEC STANDARD, Low Power Double Data Rate (LPDDR) SDRAM Specification, JESD79-4, May 2006
The MPC5121e/MPC5123 supports the configuration of two output drive strengths for DDR2 and LPDDR:
full drive strength
half drive strengh (intended for ligther loads or point-to-point environments)
The MPC5121e/MPC5123 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory
device.
This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in the DC Electrical
Characteristics.
tS_POR_CONF
Reset configuration setup time before assertion of PORESET
1 cycle
A3.14
tH_POR_CONF
Reset configuration hold time after assertion of PORESET
1 cycle
A3.15
tHR_SR_DELAY
Time from falling edge of HRESET to falling edge of SRESET
4 cycles
A3.16
tHRHOLD
Time HRESET must be held low before a qualified reset occurs
4 cycles
A3.17
tSRHOLD
Time SRESET must be held low before a qualified reset occurs
4 cycles
A3.18
tSRMIN
Time SRESET is asserted after it has been qualified
1 cycles
A3.19
Table 19. IPIC Input AC Timing Specifications1
1 T is the IP bus clock cycle. T= 12 ns is the minimum value (for the maximum IP bus freqency
of 83 MHz).
Description
Symbol
Min
Unit
SpecID
IPIC inputs - minimum pulse witdh
tPICWID
2T
ns
A4.1
Table 18. Reset Timing (continued)
Symbol
Description
Value
SYS_XTALI
SpecID
Preliminary
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