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參數(shù)資料
| 型號： | MPC5123VY300BR |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PBGA516 |
| 封裝： | 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, TFBGA-516 |
| 文件頁數(shù)： | 73/86頁 |
| 文件大小： | 719K |
| 代理商： | MPC5123VY300BR |
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System Design Information
MPC5121E/MPC5123 Data Sheet, Rev. 3
Freescale Semiconductor
75
3.3.24
VIU
The Video Input Unit (VIU) is an interface which accepts the ITU656 format compatible video stream.
Figure 56. VIU Interface Timing Diagram
4
System Design Information
4.1
Power Up/Down Sequencing
Power sequencing between the 1.4 V power supply VDD_CORE and the remaing supplies is required to prevent excessive
current during power up phase.
The recommended power sequence is as follows:
Use 12V/millisecond or slower time for all supplies.
Power up VDD_IO, PLL_AVDD, VBAT_RTC (if not applied permanently), VDD_MEM_IO, AVDD_FUSERD, USB
PHY & SATA PHY supplies first in any order and then power up VDD_CORE. If required AVDD_FUSEWR should
be powered up afterwards.
All the supplies must reach the specified operating conditions before the PORESET can be released.
For power down, drop AVDD_FUSEWR to 0V first, drop VDD_CORE to 0V, and then drop all other supplies.
VDD_CORE should not exceed VDD_IO, VDD_MEM_IO, VBAT_RTC or PLL_AVDDs by more than 0.4 V at any
time, including power-up.
4.2
System and CPU Core AVDD Power Supply Filtering
Each of the independent PLL power supplies require filtering external to the device. The following drawing Figure 57 is a
recommendation for the required filter circuit.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from
nearby circuits.
All traces should be as low impedance as possible, especially ground pins to the ground plane.
Table 51. VIU Interface Timing Parameters
Parameter
Description
Min
Typ
Max
Unit
SpecID
fPIX_CK
VIU Pixel Clock Frequency
-
83
MHz
A24.1
tDSU
VIU Data Setup Time
2.5
-
ns
A24.2
tDHD
VIU Data Hold Time
2.5
-
ns
A24.3
fPIX_CLK
tDHD
tDSU
VIU_PIX_CLK
VIU_DATA[9:0]
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC5123VY400B | 功能描述:微處理器 - MPU TELEMATICS PROCESSOR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC5123VY400BR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:e300 Power Architecture processor core |
| MPC5123YVY300B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Advance Information |
| MPC5123YVY300BR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Advance Information |
| MPC5123YVY400B | 功能描述:微處理器 - MPU TELEMATICS PROCESSOR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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