參數(shù)資料
型號： MPC5123VY300BR
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, TFBGA-516
文件頁數(shù)： 40/86頁
文件大?。?/td> 719K
代理商： MPC5123VY300BR
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 3
Freescale Semiconductor
45
Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate
data transfer rates. Adequate data transfer rates are a function of the following:
The MPC5121e/MPC5123 operating frequency (IP bus clock frequency)
Internal MPC5121e/MPC5123 bus latencies
Other system load dependent variables
The ATA clock is the same frequency as the IP bus clock in MPC5121e/MPC5123. See the MPC5121e/MPC5123 Reference
Manual.
NOTE
All output timing numbers are specified for nominal 50 pF loads.
3.3.9.1
PATA Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation of the ATA interface
in silicon, the bus transceiver used, the cable delay and cable skew. The parameters shown in Table 3-25 specify the ATA timing.
Table 3-25. PATA Timing Parameters
Name
Meaning
Controlled by
Value
SpecID
T
PATA Bus clock period
MPC5121E/M
PC5123
15 ns
A9.1
ti_ds
Set-up time ATA_DATA to ATA_IORDY edge (UDMA-in only)
MPC5121E/M
PC5123
2 ns
A9.2
ti_dh
Hold time ATA_IORDY edge to ATA_DATA (UDMA-in only)
MPC5121E/M
PC5123
5 ns
A9.3
tco
Propagation delay bus clock L-to-H to: ATA_CS0, ATA_CS1, ATA_DA2,
ATA_DA1, ATA_DA0, ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA,
ATA_BUFFER_EN
MPC5121E/M
PC5123
2 ns
A9.4
tsu
Set-up time ATA_DATA to bus clock L-to-H
MPC5121E/M
PC5123
2 ns
A9.5
tsui
Set-up time ATA_IORDY to bus clock H-to-L
MPC5121E/M
PC5123
2 ns
A9.6
thi
Hold time ATA_IORDY to bus clock H to L
MPC5121E/M
PC5123
2 ns
A9.7
tskew1
Max difference in propagation delay bus clock L-to-H to any of following
signals: ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR,
ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE), ATA_BUFFER_EN
MPC5121E/M
PC5123
1.7 ns
A9.8
tskew2
Max difference in buffer propagation delay for any of following signals:
ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR,
ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE), ATA_BUFFER_EN
Transceiver
A9.9
tskew3
Max difference in buffer propagation delay for any of following signals:
ATA_IORDY, ATA_DATA (read)
Transceiver
A9.10
tbuf
Max buffer propagation delay
Transceiver
A9.11
tcable1
Cable propagation delay for ata_data
Cable
A9.12
tcable2
Cable propagation delay for control signals: ATA_DIOR, ATA_DIOW,
ATA_IORDY, ATA_DMACK
Cable
A9.13
相關(guān)PDF資料
PDF描述
SPC5121YVY400BR RISC PROCESSOR, PBGA516
MPC601CQ50A RISC PROCESSOR
MPC601CQ66A 32-BIT, 66 MHz, RISC PROCESSOR, CQFP304
MPC604ERX300XX RISC PROCESSOR, CBGA255
MPC7410RX550PE 32-BIT, 550 MHz, RISC PROCESSOR, CBGA360
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC5123VY400B 功能描述:微處理器 - MPU TELEMATICS PROCESSOR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC5123VY400BR 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:e300 Power Architecture processor core
MPC5123YVY300B 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Advance Information
MPC5123YVY300BR 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Advance Information
MPC5123YVY400B 功能描述:微處理器 - MPU TELEMATICS PROCESSOR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*