參數(shù)資料
型號： MPC107APX100L0
廠商： MOTOROLA INC
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PPGA503
封裝： PLASTIC, BGA-503
文件頁數(shù)： 6/46頁
文件大小： 585K
代理商： MPC107APX100L0
14
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.3.1 Clock AC Specications
Table 8 provides the clock AC timing specications as dened in Section 1.4.3.2.
Notes:
1
These specications are for the default driver strengths indicated in Table 4.
2
Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.
3
Specication value at maximum frequency of operation.
4
Relock time is guaranteed by design and characterization. Relock time is not tested.
5
Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and
fall times are not tested.
6
Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock
after a stable Vdd and PCI_SYNC_IN are reached during the reset sequence. This specication also applies
when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET
must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
7
DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). Tclk is the period of one
SDRAM_SYNC_OUT clock cycle in ns. tloop is the propagation delay of the DLL synchronization feedback loop
(PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded
PC board runner) corresponds to approximately 1 ns of delay. tx0 is a xed delay inherent in the design when
Table 8. Clock AC Timing Specifications
At recommended operating conditions (See Table 2.) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Num
Characteristics and Conditions 1
Min
Max
Unit
Notes
1a
Frequency of Operation (PCI_SYNC_IN)
12.5
66
MHz
8
1b
PCI_SYNC_IN Cycle Time
80
15
ns
8
2,3
PCI_SYNC_IN Rise and Fall Times
2.0
ns
2
4
PCI_SYNC_IN Duty Cycle Measured at 1.4 V.
40
60
%
5a
PCI_SYNC_IN Pulse Width High Measured at 1.4V
6
9
ns
3
5b
PCI_SYNC_IN Pulse Width Low Measured at 1.4V
6
9
ns
3
7
PCI_SYNC_IN Jitter
<150
ps
9a
PCI_CLK[04] Skew (Pin to Pin)
500
ps
9b
SDRAM_CLK[03] Skew (Pin to Pin)
350
ps
9c
CPU_CLK[02] Skew (Pin to Pin)
350
ps
9d
SDRAM_CLK[03]/CPU_CLK[02] Jitter
150
ps
10
Internal PLL Relock Time
100
s
3,4,6
15
DLL Lock Range with DLL_EXTEND = 0 disabled (Default)
0
(NTclk - tloop - tx0) 7ns
7
16
DLL Lock Range with DLL_EXTEND = 1 enabled
0
(NTclk - Tclk/2 - tloop -
tx0) 7
ns
7
17
Frequency of Operation (OSC_IN)
12.5
66
MHz
8
18
OSC_IN Cycle Time
80
15
ns
8
19
OSC_IN Rise and Fall Times
5
ns
5
20
OSC_IN Duty Cycle Measured at 1.4 V.
40
60
%
21
OSC_IN Frequency Stability
100
ppm
22
OSC_IN VIH (Loaded)
TBD
V
23
OSC_IN VIL (Loaded)
TBD
V
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