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參數(shù)資料
| 型號： | MPC107APX066L0 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA503 |
| 封裝： | 35 X 35 MM, PLASTIC, BGA-503 |
| 文件頁數(shù)： | 40/44頁 |
| 文件大?。?/td> | 553K |
| 代理商： | MPC107APX066L0 |
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MPC107 Hardware Specifications (Rev B)
5
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Features
Message unit
Two doorbell registers
An extended doorbell register mechanism that facilitates interprocessor communication
through interrupts in a dual-local-processor system
Two inbound and two outbound messaging registers
I2O message controller
I2C controller with full master/slave support (except broadcast all)
Embedded programmable interrupt controller (EPIC)
Five hardware interrupts (IRQs) or 16 serial interrupts
Four programmable timers
Integrated PCI bus, CPU, and SDRAM clock generation
Programmable PCI bus, 60x, and memory interface output drivers
Dynamic power managementSupports 60x nap, doze, sleep, and suspend modes
Programmable input and output signals with watchpoint capability
Built-in PCI bus performance monitor facility
Debug features
Error injection/capture on data path
IEEE 1149.1 (JTAG)/test interface
Processor interface
Supports up to two PowerPC microprocessors with 60x bus interface
Supports various operating frequencies and bus divider ratios
32-bit address bus, 64/32-bit data bus supported at 100 MHz
Supports full memory coherency
Supports optional local bus slave
Decoupled address and data buses for pipelining of 60x accesses
Store gathering on 60x-to-PCI writes
Concurrent transactions on 60x and PCI buses supported
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