參數(shù)資料
型號(hào)： MP80C51C-16D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 89/109頁(yè)
文件大?。?/td> 10824K
代理商： MP80C51C-16D
66
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Figure 11-6. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x[1:0]
bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x[1:0] to
three: Setting the COM0A[1:0] bits to one allowes the OC0A pin to toggle on Compare Matches if the WGM02 bit is set.
This option is not available for the OC0B pin (See Table 11-3 on page 70). The actual OC0x value will only be visible on
the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing)
the OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represents special cases when generating a PWM waveform output in the
fast PWM mode. If OCR0x is set equal to BOTTOM, the output will be a narrow spike for each TOP+1 timer clock cycle.
Setting the OCR0x equal to TOP will result in a constantly high or low output (depending on the polarity of the output set
by the COM0x[1:0] bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0A to toggle its
logical level on each Compare Match (COM0A[1:0] = 1). The waveform generated will have a maximum frequency of
fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer
feature of the Output Compare unit is enabled in the fast PWM mode.
11.7.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM0[2:0] = 1 or 5) provides a high resolution phase correct PWM waveform generation
option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM
to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 1, and OCR0A when WGM0[2:0] =
5. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between
TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-counting. In inverting Output Compare
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
1
Period
2
3
OCnx
(COMnx[1:0] = 2)
(COMnx[1:0] = 3)
OCRnx Interrupt Flag Set
4
5
6
7
f
OCnxPWM
f
clk_I/O
N
TOP
1
+
-----------------------------------
=
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