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參數(shù)資料
| 型號(hào)： | MP7613 |
| 廠商： | Exar Corporation |
| 英文描述： | Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Parallel Data/Address mP Control Logic |
| 中文描述： | 八通道12位DAC陣列的D / A轉(zhuǎn)換器與放大器和輸出并行數(shù)據(jù)/地址MP控制邏輯 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 219K |
| 代理商： | MP7613 |
MP7613
8
Rev. 2.00
A standard
μ
-processor and TTL/CMOS compatible input
data port loads the data into the pre-selected DACS. If CS = 0,
the chip accesses digital data on the bus. Then address bits A0
to A2 select the appropriate DAC and LD1 loads the data into the
first-latch-bank. When all 8-channels first-latch-banks are
loaded, then LD2 enables the second-latch-bank and updates
all 8-channels simultaneously. The selected DAC becomes
transparent (activity on the digital inputs appear at the analog
output) when both LD1 = LD2 = 0.
R1 = 0 resets the first-latch-bank. R2 = 0 resets the second-
latch-bank which sets the analog output to zero volts (data =
100...00), regardless of digital inputs.
0
→
1
Function
A2
A1
A0
Table 1. Octal Parallel Data Input 14-Bit DAC Truth Table
Load Latch 1 of DAC1
Load Latch 1 of DAC2
Load Latch 1 of DAC3
Load Latch 1 of DAC4
Load Latch 1 of DAC5
Load Latch 1 of DAC6
Load Latch 1 of DAC7
Load Latch 1 of DAC8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
→
1
0
→
1
0
→
1
0
→
1
0
→
1
0
→
1
0
→
1
0
→
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Load Latch 2 of DAC1
→
8
X
X
X
1
1
0
1
1
Read Latch 1 of DAC1
Read Latch 1 of DAC2
Read Latch 1 of DAC3
Read Latch 1 of DAC4
Read Latch 1 of DAC5
Read Latch 1 of DAC6
Read Latch 1 of DAC7
Read Latch 1 of DAC8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Reset Latch 1 of DAC1
→
8
Reset Latch 2 of DAC1
→
8
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
0
X
X
Note: 1: High, 0: Low, X: Don’t Care
RD
LD1
LD2
CS
R1
R2
Note: For timing information see Electrical Characteristics
Figure 4. Simplified Parallel Logic Port
3-8
Decoder
3
8
8
8
To first latch bank enable
To switches across the first latch
bank for readback enable
To second latch bank enable
To reset all first latch bank
To reset all second latch bank
A0 to A2
LD1
CS
RD
LD2
R1
R2
8
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