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參數(shù)資料
| 型號： | MP7613 |
| 廠商： | Exar Corporation |
| 英文描述： | Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Parallel Data/Address mP Control Logic |
| 中文描述： | 八通道12位DAC陣列的D / A轉換器與放大器和輸出并行數(shù)據(jù)/地址MP控制邏輯 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 219K |
| 代理商： | MP7613 |
MP7613
7
Rev. 2.00
Data
Input/Output
Bus
Address
A0-A2
Chip Select
CS
Load Latch A
LD1
Load Latch B
LD2
1
0
1
0
1
0
1
0
1
0
+FS
–FS
Analog Output
t
DS
t
DH
t
AS
t
AH
t
CH1
t
CS1
t
LD1W
t
LD1LD2
t
LD2W
t
SD
don’t care
don’t care
Notes
(1)
Chip Select (CS) and Load LATCHA (LD1) Signals follow the same timing constraints and are interchangeable
in the above diagram.
R1 = R2 = 1.
For the case where LD2 is in the low state, analog output would respond to the falling edge of LD1 (transparent mode).
(2)
(3)
Address
A0-A2
Chip Select
CS
Data Readback
RD
Digital Output Data
D0 to D13
don’t care
t
AS
t
AH
t
CS2
t
RD
t
CH2
don’t care
HIGH-Z
HIGH-Z
t
DR
t
DA
1
0
1
0
1
0
1
0
Notes
(1)
Chip Select (CS) and Data Readback (RD) Signals follow the same timing constraints and are interchangeable
in the above diagram.
R1 = R2 = 1.
(2)
R1
R2
Reset first latch bank to
1000 . . . . .0000
t
R1W
t
R2W
Reset second latch bank to 1000 . . . . .0000 and analog
output to zero volt.
1
0
1
0
Figure 1. Loading Latch A and Updating Latch B
Figure 2. Read Back First Latch Bank of One DAC
Figure 3. Reset Operations
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相關代理商/技術參數(shù) |
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|---|---|
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| MP7614KS | 制造商:EXAR 制造商全稱:EXAR 功能描述:15 V CMOS Multiplying 14-Bit Digital-to-Analog Converter |
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