參數(shù)資料
型號: MN89305
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144
封裝: 20 X 20 MM, PLASTIC, LQFP-144
文件頁數(shù): 3/42頁
文件大?。?/td> 444K
代理商: MN89305
LSIs for Display
MN89305
11
s Pin Descriptions (continued)
3) PCI Bus Related Pins
Pin Name
I/O
Level
Function
CLK
I
5 V TTL
PCI clock
PCI bus synchronization clock. A clock frequency of up to 33 MHz can be used.
AD[31 : 0]
I/O
5 V TTL
Address data bus
Time-division multiplexed PCI address and data bus.
C/BE[3 : 0]
#
I
5 V TTL
Command/Byte enable
During the address phase, these lines indicate the command which can be a
memory access, an I/O access, a configuration access, or a read/write operation.
During the data phase, these lines function as byte enable signals.
PAR
I/O
5 V TTL
Bus parity
Either the parity input or parity output at the read command.
FRAME
#
I
5 V TTL
Cycle frame
Indicates the period during which the data transfer is performed. The transfer
cycle starts when this input goes low, and the transfer completes at the next data
transfer when this input has become high.
IRDY
#
I
5 V TTL
Initiator ready
A single data phase completes on the cycle during which both IRDY# and TRDY#
are low.
TRDY
#
O
Target ready
A single data phase completes on the cycle during which both IRDY# and TRDY#
are low.
STOP
#
O
Stop
This signal is output when this IC stopped the currently executing data transfer
halfway.
IDSEL
I
5 V TTL
Initialization device select
Chip select signal of the configuration register. The configuration register can be
accessed when this signal is high. If the AD signal is used as IDSEL, we
recommend connecting AD24 through AD31.
DEVSEL
#
O
Device select
Outputs a low level when an access request to this IC is detected.
BIOSCS
#
O
BIOS chip select
Outputs a low level when accepting an access to the video BIOS.
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