參數(shù)資料
型號: MN89305
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144
封裝: 20 X 20 MM, PLASTIC, LQFP-144
文件頁數(shù): 27/42頁
文件大?。?/td> 444K
代理商: MN89305
LSIs for Display
MN89305
33
RAS
#
CAS
#
3
4
5
6
2
1
No.
Descriptions
Min
Max
Min
Max
Unit
Memory type
EDO
Fast page Fast page
mode
1
Refresh cycle
Ta
+Tb+Tc+T
Ta
+Tb+Tc
ns
2
RAS# low-level period
(Ta
+Tb+T)6
(Ta
+Tb)6
ns
3
RAS# high-level period
Tc
4
Tc
4
ns
4
CAS# high-level period
Tc
4
(Tc
T)4
ns
5
CAS# setup time
T
6
T
6
ns
6
CAS# hold time
Ta
6
Ta
6
ns
Note) 1. T is one period of MCLK (the divided-by-2 PLL clock: 35 MHz to 65 MHz).
2. Values listed in the table apply when the external load capacitor is 30 pF. The output delay times will differ depending on
the external load capacitor.
s Electrical Characteristics (continued)
4. AC Characteristics (continued)
15) CBR Automatic Refresh Timing
Note) 1. CLK is one period of the display system clock (DCLK).
2. Values listed in the table apply when the external load capacitor is 30 pF. The output delay times will differ depending on
the external load capacitor.
RAS
#
CAS
#
1
2
No.
Descriptions
Min
Max
Unit
1
RAS# precharge time (immediately after a self refresh)
5CLK
25
ns
2
CAS# hold time (in self-refresh mode)
(CLK+2)
ns
16) CBR Self Refresh Timing
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