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參數(shù)資料
| 型號： | MN3304 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 消費家電 |
| 英文描述： | 512-Stage Ultra Low Voltage Operation BBD for Audio Signals |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 55K |
| 代理商： | MN3304 |
MN3300 Series
MN3304
512-Stage Ultra Low Voltage Operation BBD for Audio Signals
1
I
Overview
The MN3304 is a 512-stage ultra low voltage operation BBD variable
delay line in audio frequency range. The device operates on
+
3V
supply and provides a signal delay up to 25.6 ms and is suitable for
use as reverberation effect of low voltage operation audio equipment
such as portable stereo, radio cassette recorder and microphone.
I
Features
Variable signal delay of the audio signal : 0.256 to 25.6 ms
Wide range of supply voltage : 1.8 to 5.0 V
No insertion loss : L
i
=
0 dB typ.
Wide dynamic range : S/N
=
73 dB typ.
Low distortion : THD
=
0.7 % typ. (V
i
=
0.22 V
rms
)
Clock frequency range :10 to 200 kHz (1.8 V
≤
V
DD
<
4.0 V)
10 kHz to 1 MHz (4.0 V
≤
V
DD
≤
5.0 V)
N-channel 2-layer silicon gate process
8-Pin Dual-In-Line Plastic Package
I
Applications
Reverberation and echo effects of audio equipment such as radio
cassette recorder, car radio, portable radio, portable stereo, echo
microphone and Karaoke machine, etc.
Sound effect of electronic musical instruments
Variable or fixed delay of analog signals
DIP008-P-0300
Pin No.
Symbol
Pin Name
Description
1
GND
Ground pin
Connected to ground.
2
CP2
Clock input 2
Basic clock pulse is applied to transfer electric charge of BBD.
3
IN
Signal input pin
Analog signal to be delayed is input. Most suitable DC bias should be applied to this pin.
4
V
DD
V
DD
apply pin
Bias is applied to the gate of MOS transistor which is inserted in series with clock pulse
input gate of the BBD transfer gate.
Furthermore, voltage is supplied to step-up circuit.
5
V
D1
CP1
V
D1
apply pin
Clock input 1
The same phase clock pulse as CP1 is applied through capacitor.
6
Clock pulse of inverted phase to CP2 is applied.
7
OUT
Output pin
Composed signal of 1024th and 1025th stages is output.
8
V
D2
V
D2
apply pin
The same phase clock pulse as CP2 is applied through capacitor.
I
Pin Descriptions
I
Pin Assignment
1
2
MN3304
3
4
V
D2
OUT
CP1
V
D1
GND
CP2
IN
V
DD
8
7
6
5
512-Stage
BBD
8
7
IN
3
V
D2
OUT
V
D1
5
4
1
C
C
6
2
V
D
G
I
Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MN3305 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| MN3306 | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:128-Stage Ultra Low Voltage Operation BBD for Audio Signals |
| MN3307 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| MN3308 | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:2048-Stage Ultra Low Voltage Operation BBD for Audio Signals |
| MN3309 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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