參數(shù)資料
型號(hào): MN35502
廠商: PANASONIC CORP
元件分類(lèi): DAC
英文描述: D/A Converter for Digital Audio Equipment
中文描述: SERIAL INPUT LOADING, 20-BIT DAC, PDSO28
封裝: 0.375 INCH, PLASTIC, SOP-28
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 67K
代理商: MN35502
For Audio Equipment
MN35502
D/A Converter for Digital Audio Equipment
Pin Assignment
8PEM output configuration (4PEM output per channel)
Support for low-voltage (3.3-volt) operation
Choice of system clocks:
192 f
s
, 256 f
s
, 384 f
s
, 512 f
s
, 576 f
s
Choice of input data formats: left-packed, right-
packed, I
2
S
bus (16 or 20 bits, alternating channel input,
MSB first)
Applications
CD players and other digital audio equipment
Overview
The MN35502 is a CMOS digital-to-analog converter
designed especially for PCM digital audio equipment. It
features a built-in digital filter with 16/20-bit input.
It uses pulse edge modulation (PEM) and JVC advanced
noise shaping (VANS) to yield the high resolution and
low distortion ratio equivalent to those of 20-bit systems
covering the range between 0 and 20 kHz.
The chip incorporates an 8-fold oversampling digital
filter that eliminates a low-pass filter after the D/A
converter and thus greatly reduces the power consumption
of the overall D/A conversion system.
Use of single-channel 4PEM output yields a D/A
converter with a low distortion ratio and high signal-to-
noise ratio.
The chip makes a major contribution to reducing the
cost and size of CD players and other digital audio
equipment.
Features
Built-in 20-bit, 8-fold oversampling digital filter
2-fold oversampling digital filters with 3-stage cascade
configuration
Bandwidth ripple: within
±
0.0042 dB for 0 to 0.454 f
s
Cutoff band attenuation
1
±
0.454 f
s
: min. 94.8dB
2
±
0.454 f
s
: min. 77.4dB
4
±
0.454 f
s
: min. 66.8dB
Transition bandwidth
0.469 f
s
:
0.531 f
s
:
– 0.12dB
–38dB
Digital filter output: 24 bits
(Output after data compression with primary noise
shaper)
Built-in digital de-emphasis
fs=44.1 kHz 0 to 18kHz max. deviation
±
0.055dB
18 to 20kHz max. deviation 0.115dB
Built-in digital attenuation
Up/down over 32 steps
Support for double-speed operation (192 f
s
clock)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DIN
LRCK
BCK
M4
DV
DD2
CKO
DV
SS2
M1
OUT1C
OUT1B
AV
DD1
OUT1D
OUT1A
AV
SS1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RSBDN
RSBUP
M3
DV
DD1
XIN
XOUT
DV
SS1
M2
OUT2C
OUT2B
AV
DD2
OUT2D
OUT2A
AV
SS2
(TOP VIEW)
SOP028-P-0375
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