
RAM (
×××××8-bit)
ROM (
×××××8-bit)
Type
Package
External
5 K
LQFP128-P-1818C *Lead-free
MN102L360C
MN102L360C
Minimum Instruction
Execution Time
100 ns (at 4.5 V to 5.5 V, 20 MHz)
Interrupts
RESET Watchdog Timer counter 0 to 5 Fixed-length serial ch.0,1 transmission
Fixed-length serial ch.0,1 reception Timer counter 6 to 7 Timer counter 6 to 7 compare capture A
Timer counter 6 to 7 compare capture B ATC transfer finish External 0 to 7 Serial ch.0,1 transmission
Serial ch.0,1 reception NMI pin A/D conversion finish
Timer Counter
Timer counter 0: 8-bit
× 1 (timer output, event count)
Clock source 1/1, 1/128 of system clock frequency; 1/4 of low speed clock frequency;
external clock
Interrupt source timer counter 0 underflow
Timer counter 1: 8-bit
× 1 (timer output, even count, A/D conversion start)
Clock source system clock; 1/4 of low speed clock frequency; external clock; timer counter 0 output
Interrupt source timer counter 1 underflow
Timer counter 2 to 3: 8-bit
× 1 (timer output, event count, UART baud rate generation)
Clock source system clock; external clock; timer counter 0 output; timer counter 1, 2 output
Interrupt source timer counter 2, 3 underflow
Timer counter 4,5: 8-bit
× 1 (timer output, event count)
Clock source 1/4 of low speed clock frequency; external clock; timer counter 0 output;
timer counter 3, 4 output
Interrupt source timer counter 4, 5 underflow
Timer counter 6, 7: 16-bit
× 2
(timer output, event count, input capture, output compare, PWM output, 2-phase encoder input)
Clock source system clock; external clock; timer counter 4, 5 output
Interrupt source coincidence with compare capture A or at capture; coincidence with compare
capture B or at capture; underflow of timer counter 6, 7
Connectable
timer counter 0 to 5
Serial Interface
Serial 0: 7, 8-bit
× 1 (common use with UART, transfer direction of MSB/LSB selectable)
Clock source 1/16 of timer counter 2 frequency; 1/16 of timer counter 3 frequency; external
clock; 1/2 of timer counter 2 frequency
I2C mode (master transmission/reception is possible in the single master system.)
Serial 1: 7, 8-bit
× 1 (common use with UART, transfer direction of MSB/LSB selectable)
Clock source 1/16 of timer counter 2 frequency; 1/16 of timer counter 3 frequency; external
clock; 1/2 of timer counter 3 frequency
I2C mode (master transmission/reception is possible in the single master system.)
Fixed-length serial 0: 8-bit
× 1
Clock source external clock
Sending direction LSB
Fixed-length serial 1: 8-bit
× 1
Clock source external clock
Sending direction LSB
I/O Pins
83
Common use: 8 (by 4 bits), 75 (by bit)
I/O
A/D Inputs
8-bit
× 8-ch. (with S/H)
MAE00008FEM
210