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參數(shù)資料
| 型號： | MN103016K |
| 廠商： | PANASONIC CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 40 MHz, MICROCONTROLLER, CBGA239 |
| 封裝： | 13 X 13 MM, LEAD FREE, CERAMIC, FLGA-239 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 545K |
| 代理商： | MN103016K |
1
Data RAM (
×××××32-bit)
Command ROM (
×××××64-bit)
Type
Package
(Conventional Package)
256 K-byte
10 K-byte
MN103004K
MN103004K , MN103016K
QFP208-P-2828F *Lead-free , FLGA239-C-1313 *Lead-free
(QFP208-P-2828A)
Minimum Instruction
Execution Time
25 ns (at 2.7 V to 3.6 V, 40 MHz)
Interrupts
RESET IRQ
× 8 NMI Timer × 22 Input capture × 14 PWM × 4 SIF × 16 DMAC × 4 WDT
A/D System error
Timer Counter
Timer counter 0 to 3: 32-bit
× 1 (interval timer, event count, toggle output, interrupt, A/D conversion trigger)
Clock source IOCLK; IOCLK/8; IOCLK/32; external clock input; underflow of timer counter
Interrupt source underflow of timer counter 0, 1, 2, 3
Timer counter 4 to 7: 32-bit
× 1
(interval timer, event count, toggle output, interrupt, clock source for serial I/F, generation of timer synchronous
output timing)
Clock source IOCLK; IOCLK/8; IOCLK/32; external clock input; underflow of timer counter
Interrupt source underflow of timer counter 4, 5, 6, 7
Timer counter 8 to B: 32-bit
× 1
(interval timer, event count, toggle output, interrupt, clock source for serial I/F, generation of timer synchronous
output timing)
Clock source IOCLK; IOCLK/8; IOCLK/32; external clock input; underflow of timer counter
Interrupt source underflow of timer counter 8, 9, A, B
*: each of timer counters 0 to 3, 4 to 7, and 8 to B can be changed to an 8-, 16-, or 24-bit timer counter.
Timer counter 10 to 13: 16-bit
× 4 (interval timer, event count, toggle output, interrupt, DMA start)
Clock source IOCLK; IOCLK/8; IOCLK/32; external clock input;
underflow of timer counter 0, 1, 2
Interrupt source underflow of timer counter 10, 11, 12, 13
Timer counter 14, 15: 16-bit
× 2
(interval timer, event count, toggle output, PMW output, interrupt, input capture (2 lines), one-shot output,
external trigger start, generation of timer synchronous output timing, DMA start)
Clock source IOCLK; IOCLK/8; external clock input (2 lines);
underflow of timer counter 0, 1; 2-phase encode
Interrupt source overflow of timer 14, 15; underflow of timer 14, 15; coincidence of compare
register with binary counter or at capture
Watchdog timer: 16- to 25-bit
× 1
DMA Controller
Number of channels: 2
Unit of transfer: 8/16/32 bits
Max. Transfer cycles: 65535
Staring factor: external interrupt, timer factor, PNM factor, serial transmission/reception factor,
A/D conversion finish, software factor
Transfer method: 2-bus cycle transfer
Adressing modes: fixed, increment, decrement
Transfer modes: word transfer, burst transfer, intermittent transfer
256 K-byte
MN103016K
10 K-byte
FLGA239-C-1313 *Lead-free
MAF00004DEM
Ma
int
en
an
ce
/
Dis
co
nti
nu
ed
Maintenance/Discontinued
includes
following
four
Product
lifecy
cle
stage.
planed
maintenance
type
maintenance
type
planed
discontinued
typed
discontinued
type
Please
visit
following
URL
about
latest
information.
http://panasonic.net/sc/en
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