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參數(shù)資料
| 型號： | MN101DF08G |
| 廠商： | PANASONIC CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MN101D08E |
| 中文描述： | 8-BIT, FLASH, 14.32 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 14 MM, LEAD FREE, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 312K |
| 代理商： | MN101DF08G |
MAD00032EEM
MN101D08E
Type
Internal ROM type
ROM (byte)
RAM (byte)
Package (Lead-free)
MN
101
D
08
E
Mask ROM
80
K
2
K
MN
101
DF
08
G
FLASH
128
K
4
K
LQFP
080
-P-
1414
A
Minimum Instruction
Execution Time
[With main clock operated]
0
.
1397
μ s (at
4
.
0
V to
5
.
5
V,
14
.
32
MHz)
71
.
5
μ s (at
2
.
7
V to
5
.
5
V,
14
.
32
MHz internal
frequency di Vision)
[When sub-clock operated]
61
μ s (at
2
.
5
V to
5
.
5
V,
32
.
768
kHz)
0
.
1397
μ s (at
4
.
0
V to
5
.
5
V,
14
.
32
MHz)
71
.
5
μ s (at
2
.
7
V to
5
.
5
V,
14
.
32
MHz internal
frequency di Vision)
61
μ s (at
2
.
5
V to
5
.
5
V,
32
.
768
kHz)
Interrupts
RESET, Runaway, External
0
to
4
, Timer
0
to
3
, Timer
6
, Capstan FG, Control, HSW, Cylinder(Drum) FG, Servo V-sync,
Synchronous output, OSD, XDS, Serial
1
, Serial
2
, PWM
4
, OSD V-sync
Timer Counter
Timer counter
0
:
8
-bit
×
1
(timer function)
Clock source ...............
1
/
4
,
1
/
16
of system clock frequency
nterrupt source ........... overflow of timer counter
0
Timer counter
1
:
8
-bit
×
1
(timer function, linear timer counter function)
Clock source ...............
1
/
4
of system clock frequency; CTL signal
nterrupt source ........... overflow of timer counter
1
Timer counter
2
:
16
-bit
×
1
(timer function, input capture (CTL specified edge), duty judgment of CTL signal)
Clock source ...............
1
/
4
,
1
/
16
,
1
/
24
of system clock frequency
nterrupt source ........... overflow of timer counter
2
; input of CTL specified edge; underflow of timer
2
shift register
4
-bit counter;
coincidence of timer
2
shift register with timer
2
shift register compare register
Timer counter
3
:
16
-bit
×
1
(timer function)
Clock source ...............
1
/
4
,
1
/
16
of system clock frequency
nterrupt source ........... overflow of timer counter
3
Timer counter
5
:
19
-bit
×
1
(watchdog, stable oscillation waiting function)
Clock source ............... system clock
Watchdog interrupt source
..
1
/
2
1
6
1
/
2
1
9
of timer counter
5
frequency
Clear by stable oscillation
... after
256
counts by timer counter
5
(
2
1
8
counts of OSC oscillation clock)
Timer counter
6
:
16
-bit
×
1
(clock function [max.
2
s])
Clock source ...............
1
/
512
of OSC oscillation clock frequency; XI oscillation clock;
1
/
8
,
1
/
128
of system clock frequency
nterrupt source ...........
1
/
2
1
3
1
/
2
1
4
1
/
2
1
5
overflow of timer counter
6
Serial interface
Serial
1
:
8
-bit
×
1
(synchronous type)
(transfer direction of MSB/LSB selectable, start condition function)
Clock source ...............
1
/
8
,
1
/
16
,
1
/
32
,
1
/
64
,
1
/
128
,
1
/
256
of system clock frequency; NSBT
1
pin input
Serial
2
:
8
-bit
×
1
(I2C) (master transmission/reception, slave transmission/reception)
Clock source ...............
1
/
144
to
1
/
252
of system clock; SCK pin input
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| MN101DF09G | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:MN101D09E |
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| MN101E01K | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:MN101E01J |
| MN101E01L | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:MN101E01K |
| MN101E01M | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:MN101E01J |
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