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參數(shù)資料
| 型號： | MN101DF06ZAF |
| 廠商： | PANASONIC CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 14.32 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 18 X 18 MM, LEAD FREE, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 135K |
| 代理商： | MN101DF06ZAF |
Electrical Characteristics
Supply current
Limit
Symbol
Condition
min
typ
max
Unit
Parameter
IDD1
14.32 MHz operation without load, VDD = 5 V
60
100
mA
IDD2
1/1024 of 14.32 MHz operation without load, VDD = 3.0 V
2
5
mA
IDD3
Stop of 14.32 MHz oscillation, VDD = 2.7 V
50
100
A
32 kHz oscillation operation without load
IDSP
Stop of oscillation without load, VDD = 5 V, Ta = 55
°C10
A
IDHT0
14.32 MHz oscillation without load, VDD = 5 V
5
15
mA
IDHT1
Stop of 14.32 MHz oscillation, VDD = 2.7 V
520
A
32 kHz oscillation operation without load
(Ta = 25
°C ± 2 °C , VSS = 0 V)
Operating supply current
Supply current at STOP
Supply current at HALT
A/D Converter Performance
Limit
Symbol
Condition
min
typ
max
Unit
Parameter
NLAD
± 3
LSB
tAD
fosc = 14.32 MHz
8
s
5V
(Ta = 25
°C ± 2 °C , VDD = 5.0 V , VSS = 0 V)
Conversion relative error
A/D Conversion Time
Analog Input Voltage
XDS
Built-in U.S. closed caption data slicer (optional 2 line data can be extracted.)
ROM Correction
Correcting address designation: up to 3 addresses possible
Correction method: correction program being saved in internal RAM
I/O Pins
75
Common use: 66
I/O
2
Common use: 2
Input
A/D Inputs
8-bit
× 13-ch. (without S/H)
PWM
13-bit
× 2-ch. (at repetition cycle 572 s at 14.32 MHz),
10-bit
× 2-ch. (at repetition cycle 71.5 s at 14.32 MHz),
8-bit
× 1-ch. (at repetition cycle 71.5 s, 0.572 ms, 1.14 ms, 2.29 ms at 14.32 MHz)
ICR
18-bit
× 6-ch.
OCR
16-bit
× 2 (8-bit synchronous output; 4-bit 3-state synchronous output),
16-bit
× 1 (weak electric field V-sync backup), 16-bit × 1 (Rec CTL)
Special Ports
Buzzer output; 3-state output VLP pin; remote control receive;
CTL signal input terminal; Capstan FG inputterminal; Sylinder(Durm) PG/FG input terminals;
HSW output terminal; Head Amp/Rortary control output terminals;
output of 1/2 OSC oscillation clock (2 V[p-p]); output of 1/4 OSC oscillation clock (1 V[p-p])
MAD00029FEM
92
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