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參數(shù)資料
| 型號： | MM74HC4046SJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Phase Lock Loop |
| 中文描述： | PHASE LOCKED LOOP, 7 MHz, PDSO16 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-16 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 250K |
| 代理商： | MM74HC4046SJ |
www.fairchildsemi.com
8
M
Detailed Circuit Description
VOLTAGE CONTROLLED OSCILLATOR/SOURCE
FOLLOWER
The VCO requires two or three external components to
operate. These are R1, R2, C1. Resistor R1 and capacitor
C1 are selected to determine the center frequency of the
VCO. R1 controls the lock range. As R1
’
s resistance
decreases the range of f
MIN
to f
MAX
increases. Thus the
VCO
’
s gain increases. As C1 is changed the offset (if used)
of R2, and the center frequency is changed. (See typical
performance curves) R2 can be used to set the offset fre-
quency with 0V at VCO input. If R2 is omitted the VCO
range is from 0Hz. As R2 is decreased the offset frequency
is increased. The effect of R2 is shown in the design infor-
mation table and typical performance curves. By increasing
the value of R2 the lock range of the PLL is offset above
0Hz and the gain (Hz/Volt) does not change. In general,
when offset is desired, R2 and C1 should be chosen first,
and then R1 should be chosen to obtain the proper center
frequency.
Internally the resistors set a current in a current mirror as
shown in Figure 1. The mirrored current drives one side of
the capacitor once the capacitor charges up to the thresh-
old of the schmitt trigger the oscillator logic flips the capaci-
tor over and causes the mirror to charge the opposite side
of the capacitor. The output from the internal logic is then
taken to pin 4.
VCO WITHOUT OFFSET
R2 =
∞
VCO WITH OFFSET
FIGURE 1.
Comparator I
Comparator II & III
R
2
=
∞
R
2
≠∞
R
2
=
∞
R
2
≠∞
Given: f
0
Use f
0
with curve titled
center frequency vs R1, C
to determine R1 and C1
Given: f
0
and f
L
Calculate f
MIN
from the
equation f
MIN
=
f
o
f
L
Use f
MIN
with curve titled
offset frequency vs R2, C
to determine R2 and C1
Calculate f
MAX
/f
MIN
from
the equation f
MAX
/f
MIN
=
f
o
+
f
L
/f
o
f
L
Use f
MAX
/f
MIN
with curve
titled f
MAX
/f
MIN
vs R2/R1
to determine ratio R2/R1
to obtain R1
Given: f
MAX
Calculate f
0
from the
equation f
o
=
f
MAX
/2
Use f
0
with curve titled
center frequency vs R1, C
to determine R1 and C1
Given: f
MIN
and f
MAX
Use f
MIN
with curve titled
offset frequency vs R2,
C to determine R2 and C1
Calculate f
MAX
/f
MIN
Use f
MAX
/f
MIN
with curve
titled f
MAX
/f
MIN
vs R2/R1
to determine ratio R2/R1
to obtain R1
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| MM74HC4046 | CMOS Phase Lock Loop |
| MM74HC4046M | CMOS Phase Lock Loop |
| MM74HC4046N | CMOS Phase Lock Loop |
| MM74HC4046NX | CMOS Phase Lock Loop |
| MM74HC4049MTCX | Hex Inverting Logic Level Down Converter . Hex Logic Level Down Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM74HC4046SJ_Q | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lkd Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MM74HC4046SJX | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lkd Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MM74HC4049 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Hex Inverting Logic Level Down Converter . Hex Logic Level Down Converter |
| MM74HC4049M | 功能描述:緩沖器和線路驅(qū)動器 Hex Inv Converter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| MM74HC4049M | 制造商:Fairchild Semiconductor Corporation 功能描述:74HC CMOS SMD 74HC4049 SOIC16 |
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