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參數(shù)資料
| 型號(hào)： | MM74HC4040J |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, CDIP16 |
| 封裝： | DIP-16 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 189K |
| 代理商： | MM74HC4040J |
Absolute Maximum Ratings (Notes 2, 1)
Supply Voltage (V
CC)
0.5 to +7.0V
DC Input Voltage (V
IN)
1.5 to V
CC+1.5V
DC Output Voltage (V
OUT)
0.5 to V
CC+0.5V
Clamp Diode Current (I
CD)
±20 mA
DC Output Current, per pin (I
OUT)
±25 mA
DC V
CC or GND Current, per pin (ICC)
±50 mA
Storage Temperature Range (T
STG)
65C to +150C
Power Dissipation (P
D)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L)
(Soldering 10 seconds)
260C
Operating Conditions
Min
Max
Units
Supply Voltage (V
CC)2
6
V
DC Input or Output Voltage
0
V
CC
V
(V
IN,VOUT)
Operating Temp. Range (T
A)
MM74HC
40
+85
C
MM54HC
55
+125
C
Input Rise or Fall Times
(t
r,tf)VCC=2.0V
1000
ns
V
CC=4.5V
500
ns
V
CC=6.0V
400
ns
DC Electrical Characteristics (Note 4)
T
A=25C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A=40 to 85C
T
A=55 to
125C
Units
Typ
Guaranteed Limits
V
IH
Minimum High Level Input
2.0V
1.5
V
Voltage
4.5V
3.15
V
6.0V
4.2
V
IL
Maximum Low Level Input
2.0V
0.5
V
Voltage (Note 5)
4.5V
1.35
V
6.0V
1.8
V
OH
Minimum High Level Output
V
IN=VIH or VIL
Voltage
|I
OUT|≤20 A
2.0V
2.0
1.9
V
4.5V
4.5
4.4
V
6.0V
6.0
5.9
V
IN=VIH or VIL
|I
OUT|≤4.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|I
OUT|≤5.2 mA
6.0V
5.7
5.48
5.34
5.2
V
OL
Maximum Low Level Output
V
IN=VIH or VIL
Voltage
|I
OUT|≤20 A
2.0V
0
0.1
V
4.5V
0
0.1
V
6.0V
0
0.1
V
IN=VIH or VIL
|I
OUT|≤4.0 mA
4.5V
0.2
.26
0.33
0.4
V
|I
OUT|≤5.2 mA
6.0V
0.2
.26
0.33
0.4
V
I
IN
Maximum Input Current
V
IN=VCC or
GND
6.0V
±0.1
±1.0
A
I
CC
Maximum Quiescent Supply
V
IN=VCC or
GND
6.0V
8.0
80
160
A
Current
I
OUT=0A
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: 12 mW/C from 65C to 85C; ceramic “J” package: 12 mW/C from 100C to 125C.
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Note 5: VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
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