- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄182950 > MM74HC597SJX (FAIRCHILD SEMICONDUCTOR CORP) PDF資料下載
參數(shù)資料
| 型號： | MM74HC597SJX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 計數(shù)移位寄存器 |
| 中文描述： | HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-16 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 85K |
| 代理商： | MM74HC597SJX |
2000 Fairchild Semiconductor Corporation
DS005343
www.fairchildsemi.com
January 1988
Revised August 2000
MM74HC597
8-Bi
tShif
tRegi
ster
s
wi
th
Input
L
a
tches
MM74HC597
8-Bit Shift Registers with Input Latches
General Description
This high speed register utilizes advanced silicon-gate
CMOS technology. It has the high noise immunity and low
power consumption of standard CMOS integrated circuits,
as well as the ability to drive 10 LS-TTL loads.
The MM74HC597 comes in a 16-pin package and consists
of an 8-bit storage latch feeding a parallel-in, serial-out
8-bit shift register. Both the storage register and shift regis-
ter have positive-edge triggered clocks. the shift register
also has direct load (from storage) and clear inputs.
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
s 8-bit parallel storage register inputs
s Wide operating voltage range: 2V–6V
s Shift register has direct overriding load and clear
s Guaranteed shift frequency: DC to 30 MHz
s Low quiescent current: 80
A maximum
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Top View
Truth Table
Order Number
Package Number
Package Description
MM74HC597M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
MM74HC597SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC597N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
RCK SCK SLOAD SCLR
Function
↑
X
Data Loaded to input latches
↑
XL
H
Data loaded from inputs to
shift register
No
Data transferred from
clock
X
L
H
input latches to shift
edge
register
XX
L
Invalid logic, state of
shift register indeterminate
when signals removed
X
H
L
Shift register cleared
X
↑
HH
Shift register clocked
Qn = Qn1, Q0 = SER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MM74HCT544J | HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, CDIP24 |
| MM8001 | UHF BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR, TO-39 |
| MM82C19WM | |
| MM908E621 | Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror |
| MM9329-2700TB1 | BOARD TERMINATED, FEMALE, RF CONNECTOR, SURFACE MOUNT, RECEPTACLE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM74HC620 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal TRI-STATE Transceiver |
| MM74HC623 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal TRI-STATE Transceiver |
| MM74HC640 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Inverting Octal TRI-STATE Transceiver |
| MM74HC640AN | 制造商:Texas Instruments 功能描述: |
| MM74HC640AWM | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。